Inventors:
Mark J. Boyd - Santa Cruz CA, US
Tracy Larrabee - Santa Cruz CA, US
Assignee:
The Regents of the University of California, Santa Cruz - Oakland CA
International Classification:
G06F 17/50, G06F 9/45, H03K 11/693
US Classification:
716 5, 716 2, 716 4, 716 16
Abstract:
The application concerns prototyped custom Programmable Logic Devices (Pills) for Boolean satisfiability (SAT) problems. This approach is based on the use of clause evaluation circuits (CECs), which indicate whether or not a single variable of the clause is asserted by the clause, and variable evaluation circuits (VECs), which identify the asserted variable of a clause having exactly one variable asserted by the clause. Scaling is provided by the use of partial CEC and VEC circuits.