Mark D Larsen
Broker in Sandy, UT
License number
Utah 333526-5802
Issued Date
Jan 23, 1997
Expiration Date
May 31, 1998
Category
Preneed
Type
Pre-Need Sales Agent
Address
Address
Sandy, UT
Personal information
See more information about Mark D Larsen at radaris.comName
Address
Phone
5761 Beaumont Dr, Salt Lake Cty, UT 84121
580 S 515 W, Cedar City, UT 84720
3704 Cambridge Dr, Salt Lake Cty, UT 84119
335 E 3575 N, Ogden, UT 84414
388 Paddock Ln, Kaysville, UT 84037
Professional information
Semiconductor Dice With Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using The Same, And Methods Of Making The Same
US Patent:
8598035, Dec 3, 2013
Filed:
Jun 2, 2011
Appl. No.:
13/151495
Inventors:
Michael D. Gruenhagen - Salt Lake City UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Douglas E. Dolan - York ME, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Douglas E. Dolan - York ME, US
Assignee:
Fairchild Semiconductor Corporation - San Jose CA
International Classification:
H01L 21/44
US Classification:
438669, 438284, 438652, 257E21158, 257341, 257678
Abstract:
Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
3D Channel Architecture For Semiconductor Devices
US Patent:
8072027, Dec 6, 2011
Filed:
Jun 8, 2009
Appl. No.:
12/480065
Inventors:
Suku Kim - Singapore, SG
Dan Calafut - San Jose CA, US
Ihsiu Ho - Salt Lake City UT, US
Dan Kinzer - El Segundo UT, US
Steven Sapp - Felton CA, US
Ashok Challa - Sandy ID, US
Seokjin Jo - South Jordan UT, US
Mark Larsen - Sandy UT, US
Dan Calafut - San Jose CA, US
Ihsiu Ho - Salt Lake City UT, US
Dan Kinzer - El Segundo UT, US
Steven Sapp - Felton CA, US
Ashok Challa - Sandy ID, US
Seokjin Jo - South Jordan UT, US
Mark Larsen - Sandy UT, US
Assignee:
Fairchild Semiconductor Corporation - San Jose CA
International Classification:
H01L 29/78
US Classification:
257332, 257341, 257E29257, 257E2926
Abstract:
Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
Semiconductor Die Structures For Wafer-Level Chipscale Packaging Of Power Devices, Packages And Systems For Using The Same, And Methods Of Making The Same
US Patent:
8058732, Nov 15, 2011
Filed:
Nov 20, 2008
Appl. No.:
12/275086
Inventors:
Michael D. Gruenhagen - Salt Lake City UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Ihsiu Ho - Salt Lake City UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Rohit Dikshit - Herriman UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Ihsiu Ho - Salt Lake City UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Rohit Dikshit - Herriman UT, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 23/48
US Classification:
257774, 257773, 257698, 257E25017, 257E23145, 257E21549, 257E21577, 257E21585
Abstract:
Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
Semiconductor Dice With Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using The Same, And Methods Of Making The Same
US Patent:
7960800, Jun 14, 2011
Filed:
Dec 12, 2008
Appl. No.:
12/334331
Inventors:
Michael D. Gruenhagen - Salt Lake City UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Douglas E. Dolan - York ME, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Douglas E. Dolan - York ME, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 27/088
US Classification:
257401, 257E21585, 257417, 257673, 257678, 438106, 438284, 438286
Abstract:
Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.