MARK C JOHNSON, MD
Marriage and Family Therapists in Boise, ID

License number
Idaho M5266
Category
Osteopathic Medicine
Type
Family Medicine
Address
Address
3301 N SAWGRASS WAY, Boise, ID 83704
Phone
(208) 375-0862
(208) 375-2658 (Fax)

Personal information

See more information about MARK C JOHNSON at radaris.com
Name
Address
Phone
Mark Johnson, age 68
49 W 50 S, Blackfoot, ID 83221
(208) 251-7812
Mark Dolan Johnson, age 63
1590 Conestoga Way, Blackfoot, ID 83221
Mark Dolan Johnson, age 63
1499 Sierra Dr, Pocatello, ID 83201
Mark Dolan Johnson, age 63
2386 Gooding St, Pocatello, ID 83201
Mark Edwin Johnson, age 64
2008 N 14Th St, Coeur d Alene, ID 83814

Organization information

See more information about MARK C JOHNSON at bizstanding.com

St Luke's Mountain View Medical Center - Jerry Mulder MD

3301 N Sawgrass Way, Boise, ID 83704

Doing business as:
St Luke's Mountain View Medic - Russell M Kocemba MD<br>St Luke's Mountain View Medic - Mark C Johnson MD
Phone:
(208) 375-0862 (Phone)
Categories:
Family & General Practice Physicians & Surgeons, Physicians & Surgeons, Sports Medicine Physicians & Surgeons, ...


Mark C Johnson MD

3301 N Sawgrass Way, Boise, ID 83704

Industry:
Medical Doctor's Office
Medical Doctor, Principal:
Mark Johnson (Medical Doctor, Principal)

Professional information

See more information about MARK C JOHNSON at trustoria.com
Mark C Johnson Photo 1
Dr. Mark C Johnson - MD (Doctor of Medicine)

Dr. Mark C Johnson - MD (Doctor of Medicine)

Hospitals:
Mountain View Medical
3301 N Sawgrass Way, Boise 83704
St. Luke's Regional Medical Center
190 East Bannock St, Boise 83712
Mountain View Medical
3301 N Sawgrass Way, Boise 83704
St. Luke's Regional Medical Center
190 East Bannock St, Boise 83712
Philosophy:
Mark C. Johnson, MD is board certified in family medicine. He completed his undergraduate degree at the University of Washington in 1981 and earned his medical degree from St. Louis University in St. Louis, Missouri in 1986. He completed his residency at the Family Practice Residency of Idaho in Boise, where he also served as faculty. Dr. Johnson began private practice in 1991.
Education:
Medical Schools
Saint Louis University School Of Medicine
Graduated: 1986


Mark Johnson Photo 2
Manual Pellet Loader For Boschman Automolds

Manual Pellet Loader For Boschman Automolds

US Patent:
5925384, Jul 20, 1999
Filed:
Apr 25, 1997
Appl. No.:
8/845603
Inventors:
Todd O. Bolken - Meridian ID
Mark S. Johnson - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
B29C 3104, B29C 4502
US Classification:
425116
Abstract:
A manual loader for use in bypassing an automatic pellet feeder for an automold machine used to encapsulate integrated circuit assemblies in plastic. The loader has a support mounted adjacent the mold section of the machine. The loader also has at least one pellet boat which moves relative to the support into and out of said mold section. The pellet boat includes one or more pellet pots which are adapted to receive and hold a solid pellet of material. The loader has a release mechanism which is movable between a blocking position and a release position. The release mechanism retains the pellets in the pellet pots in the blocking position and releases the pellets from the pots when manipulated to the release position for dropping the pellets into a mold of the machine's mold section.


Mark Johnson Photo 3
Principle At Bauercaptain&Amp;Johnson

Principle At Bauercaptain&Amp;Johnson

Position:
principle at bauercaptain&johnson
Location:
Boise, Idaho Area
Industry:
Financial Services
Work:
bauercaptain&johnson - principle


Mark Johnson Photo 4
Stereolithographic Method And Apparatus For Packaging Electronic Components And Resulting Structures

Stereolithographic Method And Apparatus For Packaging Electronic Components And Resulting Structures

US Patent:
6549821, Apr 15, 2003
Filed:
Feb 26, 1999
Appl. No.:
09/259142
Inventors:
Warren M. Farnworth - Nampa ID
Mark S. Johnson - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 1900
US Classification:
700120, 700119, 264163, 26427214, 26427215, 26427217
Abstract:
A stereolithographic method and apparatus for applying packaging material to workpieces such as preformed electronic components, including semiconductor dice, with a high degree of precision, and resulting articles. A machine vision system including at least one camera is operably associated with a computer controlling a stereolithographic system for application of material so that the system may recognize the position and orientation of workpieces, such as semiconductor dice, to which the material is to be applied. The requirement for precise mechanical workpiece alignment is eliminated, and the ability of the system to recognize size, configuration and topography of different workpieces affords greater manufacturing flexibility. The method includes stereolithographic application of material for packaging electronic components, and the electronic components so packaged are also part of the invention.


Mark Johnson Photo 5
Asymmetric Transfer Molding Method And An Asymmetric Encapsulation Made Therefrom

Asymmetric Transfer Molding Method And An Asymmetric Encapsulation Made Therefrom

US Patent:
6605331, Aug 12, 2003
Filed:
Sep 1, 1999
Appl. No.:
09/388045
Inventors:
Mark S. Johnson - Boise ID
Todd O. Bolken - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
B32B 302
US Classification:
428 76, 428 357, 425116, 425117, 425127, 4251291
Abstract:
A method of encapsulating an article having first and second surfaces, includes positioning a first molding section in a sealing relationship with the first surface of the article and positioning a second molding section adjacent the second surface of the article. The first molding section is filled first thereby forcing the second surface of the article into a sealing engagement with the second molding section. The second molding section is then filled.


Mark Johnson Photo 6
Method For Making A Packaged Semiconductor Device

Method For Making A Packaged Semiconductor Device

US Patent:
6601294, Aug 5, 2003
Filed:
Sep 29, 2000
Appl. No.:
09/672690
Inventors:
Tongbi Jiang - Boise ID
Mark S. Johnson - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H05K 330
US Classification:
29841, 29840, 29848, 26427211, 361717
Abstract:
A semiconductor package with thermally enhanced properties is described. The semiconductor package includes a substrate upon which a die is affixed. The die and the substrate each have contacts which are respectively connected with each other. A heat sink is affixed to a surface of the die by way of a thermally compliant material. The compliant material reduces the stresses caused by temperature fluctuations which cause the heat sink and the die to expand and contract at different rates. A first molding material is deposited around the periphery of the die, compliant material and heat sink, thereby leaving exposed substantially an entire surface of the heat sink.


Mark Johnson Photo 7
Precision Fiducial

Precision Fiducial

US Patent:
6632575, Oct 14, 2003
Filed:
Aug 31, 2000
Appl. No.:
09/654107
Inventors:
Mark S. Johnson - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G03F 900
US Classification:
430 5, 430 22
Abstract:
A fiducial includes complementary patterns that are situated symmetrically about a common axis. The complementary patterns permit location of the common axis as an axis that is equidistant from the complementary patterns. The complementary patterns are displaced from the common axes by different distances so that the common axis is located using the complementary patterns nearest the common axis to accurately locate the common axis. The complementary patterns include etch-compensation features that permit the common axis to be accurately located even if an etch process defines the fiducial and the etch process exhibits a process error or variation such as underetching or overetching. The fiducial may be produced by transferring a fiducial pattern from a mask such as a photomask. The fiducial pattern may also be defined on the mask using a computer-aided design program.


Mark Johnson Photo 8
Semiconductor Package Having Exposed Heat Dissipating Surface And Method Of Fabrication

Semiconductor Package Having Exposed Heat Dissipating Surface And Method Of Fabrication

US Patent:
7151013, Dec 19, 2006
Filed:
Oct 1, 2002
Appl. No.:
10/260615
Inventors:
David J. Corisis - Meridian ID, US
Mike Brooks - Caldwell ID, US
Mark S. Johnson - Boise ID, US
Larry D. Kinsman - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/44
US Classification:
438127, 438122, 438124, 257666, 257787, 257E25011
Abstract:
A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being attached to a respective semiconductor die. The dies are attached to respective lead frames via an adhering material, such as a tape. Further, the dies are each electrically connected to fingers of each lead frame. In one illustrated embodiment, the dies and portions of the fingers are encapsulated in such a way as to leave one surface of each die exposed. In another illustrated embodiment, heat dissipation for the semiconductor package occurs through exposed fingers of the lead frames which adhere semiconductor dies within a cavity located therebetween.


Mark Johnson Photo 9
Plating Buss And A Method Of Use Thereof

Plating Buss And A Method Of Use Thereof

US Patent:
7608788, Oct 27, 2009
Filed:
Oct 9, 2007
Appl. No.:
11/869204
Inventors:
Mark S. Johnson - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01R 12/04, H05K 1/11
US Classification:
174261
Abstract:
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.


Mark Johnson Photo 10
Overmolding Encapsulation Process And Encapsulated Article Made Therefrom

Overmolding Encapsulation Process And Encapsulated Article Made Therefrom

US Patent:
7655508, Feb 2, 2010
Filed:
Jul 20, 2004
Appl. No.:
10/894675
Inventors:
Mark S. Johnson - Boise ID, US
Todd O. Bolken - Meridian ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/00
US Classification:
438127, 438112, 257E21503
Abstract:
A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first surface contacts the carrier. A portion of the carrier carrying the article is then positioned within a mold and a seal is formed between the mold and the carrier. The mold is then filled with an encapsulating material to form a seal between the article and the carrier.