MARK ALAN JOHNSON
Pilots at 2 St, San Jose, CA

License number
California C1070386
Category
Airmen
Address
Address
350 N 2Nd St APT 331, San Jose, CA 95112

Professional information

Mark Johnson Photo 1

Mark Johnson - San Jose, CA

Work:
Electronics and Shell
Sr. Mechanical Engineer
Electronics and Shell
Senior Project Manager /Estimator/ Mechanical Engineer /Business Development
Electronics and Shell
Director of Business Development - Mechanical Division
Electronics and Shell
Business Development Consultant
Electronics and Shell
Business Development / Engineering Manager
Electronics and Shell - Silicon Valley, CA
Senior Project Manager / Estimator
Electronics and Shell
Senior Account Executive
Electronics and Shell
Senior Account Executive / Business Development / Marketing
Electronics and Shell
Project Manager / Mechanical Engineer / Estimator
Electronics and Shell
Project Manager / Mechanical Engineer / Estimator
Electronics and Shell
Project Manager / Business Development
Electronics and Shell
Mechanical Designer / Project Engineer


Mark Johnson Photo 2

Mark Johnson - San Jose, CA

Work:
Nanosolar, Inc
SEM TECHNICIAN
SPACE SYSTEMS/ LORAL - Palo Alto, CA
DPA Technician
QUALIFIED PARTS LAB - San Jose, CA
TEST TECHNICIAN


Mark Johnson Photo 3

Systems And Methods For Verifying Recovery From An Intermittent Hardware Fault

US Patent:
2008023, Oct 2, 2008
Filed:
Mar 29, 2007
Appl. No.:
11/693206
Inventors:
Joe S. Hsu - San Jose CA, US
Mark C. Johnson - San Jose CA, US
Hugh W. McDevitt - San Jose CA, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G01R 31/08
US Classification:
370216
Abstract:
Systems and methods for verifying recovery from intermittent hardware faults. Exemplary embodiments include a method for verifying recovery from intermittent hardware faults, the method including generating an error in a computer interface by forcing a hardware fault after setting an error injection enable control bit in a register coupled to the computer interface, detecting an error in a hardware checker coupled to the computer interface which asserts an error interrupt signal resetting the error injection enable control bit when the error interrupt signal and a hardware reset control bit coupled to the computer interface are both active, disabling error forcing when the error injection enable control bit is reset, and executing an error recovery and logging procedure in the computer interface.


Mark Johnson Photo 4

Method And Apparatus For Parallel And Pipelining Transference Of Data Between Integrated Circuits Using A Common Macro Interface

US Patent:
5845072, Dec 1, 1998
Filed:
May 5, 1997
Appl. No.:
8/850284
Inventors:
Damon W. Finney - San Jose CA
Wen-Jei Ho - Saratoga CA
Mark C. Johnson - San Jose CA
Donald J. Lang - Cupertino CA
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
39520038
Abstract:
A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.


Mark Johnson Photo 5

Apparatus, System, And Method For Managing Errors In Prefetched Data

US Patent:
7437593, Oct 14, 2008
Filed:
Jul 14, 2003
Appl. No.:
10/619816
Inventors:
Mark C. Johnson - San Jose CA, US
Bitwoded Okbay - Gilroy CA, US
Andrew Moy - San Jose CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 2, 714 42, 714 52, 714776, 370463
Abstract:
An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.


Mark Johnson Photo 6

Distributed Trace Data Acquisition System

US Patent:
5642478, Jun 24, 1997
Filed:
Dec 29, 1994
Appl. No.:
8/366185
Inventors:
Chin-Huang Chen - San Jose CA
Mark C. Johnson - San Jose CA
Donald John Lang - Cupertino CA
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1108
US Classification:
39518321
Abstract:
A dedicated debugging facility for tracing hardware and software faults in a distributed digital system. An event data capture circuit is integrated into each processing node in a distributed multinode system for capturing event data within each node under software control. The captured event data is stored in one of a plurality of variable-length trace data buffers in the node processor memory space for analysis or transfer. These dedicated trace data acquisition circuits provide continuously available trace data for the hardware and software functions within each node. Each variable-length trace data entry is stored in the trace data buffers according to a format of this invention that permits collection and assembly of trace data entries from throughout the distributed multinode system to debug local hardware or software and to debug internodal interconnection hardware and software.


Mark Johnson Photo 7

Reactor Useful For Chemical Vapor Deposition Of Titanium Nitride

US Patent:
6106625, Aug 22, 2000
Filed:
Feb 13, 1998
Appl. No.:
9/023852
Inventors:
Keith Koai - Los Gatos CA
Mark Johnson - San Jose CA
Mei Chang - Saratoga CA
Lawrence Chung Lei - Milpitas CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
118715
Abstract:
A plasma reaction chamber particularly configured for chemical vapor deposition of titanium nitride with a TDMAT precursor, the deposition including a plasma step. Gas is injected from a gas cavity in a showerhead electrode assembly through a large number of showerhead holes into the processing region over the wafer. The showerhead electrode is capable of being RF energized to create a plasma of a gas in the processing region. The showerhead electrode and other parts of the assembly are cooled by a cooling plate disposed above the gas cavity and connected to a rim of the showerhead electrode. A convolute water-cooling channel is formed in the cooling plate having a small cross section and numerous bends so as to create turbulent flow, thus aiding thermal transfer. The water cooling plate is connected to the showerhead electrode across a large horizontal interface, thus also aiding thermal flow. An edge ring assembly is positioned in a peripheral recess at the top of heater pedestal supporting the wafer next to the processing region.


Mark Johnson Photo 8

Apparatus And Method For Controlling A Flow Of Process Material To A Deposition Chamber

US Patent:
6176930, Jan 23, 2001
Filed:
Mar 4, 1999
Appl. No.:
9/262756
Inventors:
Keith K. Koai - Los Gatos CA
Tung-Ching Tseng - Sunnyvale CA
James J. Chen - San Jose CA
Mark S. Johnson - San Jose CA
John Schmitt - Sunnyvale CA
Sean Li - Sunnyvale CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
118715
Abstract:
An apparatus and method for controlling a flow of process material to a deposition chamber. The apparatus comprises an injector valve, disposed between the process material source and the deposition chamber. The injector valve controls the flow of precursor material by repeatedly opening and closing the injector valve with a predetermined duty cycle. The apparatus further comprises an evaporator coupled to the injector valve for evaporating the precursor.


Mark Johnson Photo 9

Multilevel Birdbath And Removable Liner

US Patent:
2013003, Feb 14, 2013
Filed:
Oct 16, 2012
Appl. No.:
13/653357
Inventors:
Mark V. Johnson - San Jose CA, US
International Classification:
A01K 45/00, B23P 23/00
US Classification:
119 695, 294011
Abstract:
A multilevel birdbath consists of a main body that has a concave, contoured inside surface and an exterior lower surface, the main body further has a flat rim surrounding the concave inside surface and the concave inside surface optionally has stepped areas fluctuating in height and a sloping portion such that the stepped areas would create different depths of the multilevel birdbath which can accommodate and attract birds of different sizes and species.


Mark Johnson Photo 10

Multilevel Bird Bath

US Patent:
D669230, Oct 16, 2012
Filed:
Oct 18, 2010
Appl. No.:
29/377189
Inventors:
Mark V. Johnson - San Jose CA, US
International Classification:
3007
US Classification:
D30123