Mark A. Lysinger
Engineering in Carrollton, TX

5566112, Oct 15, 1996

Aug 10, 1994

8/288334

Mark A. Lysinger - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

G11C 702

365196

An apparatus generates a bus-driver enable signal that enables a bus driver to couple a data signal from a sense amplifier to a data bus. A first circuit generates an equilibration pulse to equilibrate the sense amplifier, and a bus-driver enable circuit generates the bus-driver enable signal. A bus-driver disable circuit generates in response to the equilibration pulse a bus-driver disable signal for disabling the enable circuit at least until the data signal becomes valid.

7196922, Mar 27, 2007

Jul 25, 2005

11/188396

Mark Lysinger - Carrollton TX, US

STMicroelectronics, Inc. - Carrollton TX

G11C 15/00, G11C 7/00

365 49, 36518907, 36518908

A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated with respective rows. A plurality of encoder cells, each having a memory element and forming an encoder block are arranged in rows. Precharged bus lines are operative with the encoder cells and match lines. The precharged bus lines are discharged indicating a match and priority is assigned to rows based on logic values stored within the memory elements of the encoder cell.

6373737, Apr 16, 2002

Jun 7, 1995

08/478429

Mark A. Lysinger - Carrollton TX

STMicroelectronics, Inc. - Carrollton TX

G11C 1504

365 49, 36518907

A content addressable memory includes a memory array having a plurality of entries. Control circuitry is provided for sequentially presenting each entry in the array to a comparator. An input signal is also provided to the comparator. Entries matching the input signal are identified for later use. The input signal can be masked, so that only selected fields of each entry are compared to it. Conventional RAM technology can be used for the memory array. In the alternative, a serial memory array, such as an array formed from a charge coupled device, can be used.

7688669, Mar 30, 2010

Feb 11, 2008

12/029366

David C. McClure - Carrollton TX, US
Mark A. Lysinger - Carrollton TX, US
Mehdi Zamanian - Carrollton TX, US
François Jacquet - Froges, FR
Philippe Roche - Le Versoud, FR

STMicroelectronics, Inc. - Carrollton TX
STMicroelectronics SA

G11C 7/00

365226, 36518909, 365229

A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

4974241, Nov 27, 1990

Mar 31, 1989

7/332290

David C. McClure - Carrollton TX
Mark A. Lysinger - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

H03K 2102, H03K 2344

377116

The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

2008021, Sep 4, 2008

Feb 8, 2008

12/028504

Mark A. Lysinger - Carrollton TX, US
Naren Sahoo - Carrollton TX, US

STMicroelectronics, Inc. - Carrollton TX

H01H 85/30

324550

An integrated circuit includes at least one circuit trimming fuse. A fuse sensor circuit is connected to the trimming fuse and operates in response to a fuse sensing initiation signal to initiate sensing of a state of the trimming fuse and generate an output indicative of the sensed state. A latch circuit, including multiple latch locations, redundantly latches the output indicative of the sensed state. A majority logic state in the latch locations is determined by a polling circuit coupled to the multiple latch locations. The polling circuit outputs that majority logic state as a fuse state output indicative of the sensed state of the fuse. A register in the integrated circuit is loadable with a value. A comparison circuit compares the loaded value in the register to a correct fuseword value and, if there is a match, generates the fuse sensing initiation signal for application to the fuse sensor circuit.

5311467, May 10, 1994

Apr 7, 1992

7/864481

Mark A. Lysinger - Carrollton TX
William C. Slemmer - Dallas TX
James Brady - Dallas TX
David C. McClure - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

G11B 700

36518901

A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

5805523, Sep 8, 1998

Apr 4, 1997

8/825971

Mark A. Lysinger - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

G11C 800

36523008

The decoded address signal is stored in the slave latch. The output of the slave latch is a column select signal. The slave latches are organized in a slave latch circuit which is connected as a counter. Each of the slave latches is treated as a register and four slave latches are combined to permit the sequential addresses selected to be in count up or count down as the slave latch circuit is clocked. In addition, a burst counter control circuit selectively controls the counter to produce a count in an interleaved mode or a count up mode. The least significant bit of the address is stored within the burst control circuit for indicating whether the count should be an up count or a down count when operating in the interleaved mode.

5267210, Nov 30, 1993

Mar 3, 1993

8/025894

David C. McClure - Carrollton TX
Mark A. Lysinger - Carrollton TX

SGS-Thomson Microelectronics, Inc. - Carrollton TX

G11C 1140

365218

A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.

8482964, Jul 9, 2013

Dec 22, 2009

12/645039

Kevin K. Walsh - Peoria AZ, US
Paul F. Gerrish - Phoenix AZ, US
Larry E. Tyler - Mesa AZ, US
Mark A. Lysinger - Carrollton TX, US
David C. McClure - Carrollton TX, US
Francois Jacquet - Crolles, FR

STMicroelectronics, Inc. - Coppell TX
STMicroelectronics SA - Montrouge
Medtronic, Inc. - Tempe AZ

G11C 11/00

365154, 365156, 365149, 36518909

An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.