LUU PHUONG NGUYEN, PHARM. D.
Pharmacy at King Rd, San Jose, CA

7824963, Nov 2, 2010

Nov 25, 2009

12/626440

Randall L. Walberg - Campbell CA, US
Luu T. Nguyen - San Jose CA, US
Anindya Poddar - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 21/44, H01L 23/495

438111, 257676

Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.

5437095, Aug 1, 1995

Dec 21, 1993

8/171713

Luu T. Nguyen - San Jose CA
Hem P. Takiar - Fremont CA

National Semiconductor Corporation - Santa Clara CA

H01R 4300

29827

A method of making an integrated circuit package is disclosed herein along with the package itself, which package is encapsulated by plastic that is caused to flow in a given direction during the package's formation. The package itself includes an IC chip having an army of chip output/input terminals, and means for supporting the chip including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip. In addition, the overall package includes bonding wires connecting the chip output/input terminals with respective ones of the leads such that each bonding wire extends in a direction that defines an acute angle of less than 45 degrees with the given flow direction of the plastic material used to encapsulate the IC chip, support means and bonding wires. In a preferred embodiment, at least a portion and most preferably substantially all of the bonding wires are substantially parallel with the given flow direction of the plastic material.

7808089, Oct 5, 2010

Dec 18, 2007

11/959412

Luu T. Nguyen - San Jose CA, US
Vijaylaxmi Gumaste - Santa Clara CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/495

257676, 257E23043, 257666, 257667, 438106

One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of the pedestals. Selected edge regions of the die are arranged to overlie recessed regions of the die attach pad between adjacent pedestals. The die is electrically connected to at least some of the contact leads. An adhesive is arranged to secure the die to the die attach pad, with the thickness of the adhesive between the web of the die attach pad and the die being greater than the thickness of the adhesive between the die and the top surfaces of the pedestals that support the die. The die attach pad may have rounded peripheral corners between adjacent edge surfaces of the die attach pad. In another aspect of the invention, a method of packaging integrated circuits is described, wherein the resulting packages include at least some of the aforementioned leadframe structures.

5328079, Jul 12, 1994

Mar 19, 1993

8/034683

Ranjan J. Mathew - San Jose CA
Arnold Smith - San Jose CA
Luu T. Nguyen - San Jose CA

National Semiconductor Corporation - Santa Clara CA

H01R 4302, H01L 2160

2281805

Certain components of an integrated circuit package are disclosed herein including one or more dies, each of which has an array of die output/input bond pads, and die support means, for example a substrate or leadframe, which includes an array of electrically conductive leads. There is also disclosed herein a technique for wire bond connecting the bond pads of a particular die to either the bond pads of a second die or to the electrically conductive leads of the substrate or leadframe using a thermosonic or thermocompression ball bonding tool. In accordance with this technique, where at least one die is involved, connections are made to the bond pads of that die by means of stitch bonding in a way which does not damage the die.

5422435, Jun 6, 1995

May 22, 1992

7/887774

Hem P. Takiar - Fremont CA
Peng-Cheng Lin - Cupertino CA
Luu T. Nguyen - San Jose CA

National Semiconductor Corporation - Santa Clara CA

H01L 2302

174 524

A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.

7098540, Aug 29, 2006

Dec 4, 2003

10/729389

Jitendra Mohan - Santa Clara CA, US
Luu Nguyen - San Jose CA, US
Alan Segervall - Half Moon Bay CA, US
Stephen Gee - Danville CA, US

National Semiconductor Corporation - Santa Clara CA

H01L 23/48, H01L 23/52, H01L 29/40

257773, 257737, 257778

The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds the first support structure on the substrate. The first and second support structures are each configured to support an electrical connector to be formed over the first and second support structures on the substrate.

2013012, May 23, 2013

Nov 23, 2011

13/304167

Anindya Poddar - Sunnyvale CA, US
Luu T. Nguyen - San Jose CA, US

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

H01L 21/60, H01L 23/482

257522, 438123, 257E21573, 257E23013, 257E21506

In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.

2006005, Mar 16, 2006

Nov 3, 2005

11/267719

Ken Pham - San Jose CA, US
Luu Nguyen - San Jose CA, US
William Mazotti - San Martin CA, US

National Semiconductor Corporation - Santa Clara CA

B29C 45/02, B29C 45/14, B29C 45/37, B29C 70/72, B29C 70/88, H01L 21/56

264276000, 264272150, 264272170

Techniques for forming packaged semiconductor devices having top surfaces with flash-free electrical contact surfaces are described. According to one aspect, a molding cavity is provided which has a molding surface that is sufficiently smooth such that when placed in contact with an electrically conductive contact, gaps between the conductive contact and the mold cavity surface do not form.

2012021, Aug 30, 2012

Feb 28, 2011

13/037281

Peter J. Hopper - San Jose CA, US
Peter Johnson - Sunnyvale CA, US
Luu Nguyen - San Jose CA, US
Peter Smeys - San Jose CA, US

H01L 29/02, H01L 21/762

257506, 438455, 257622, 257E29002, 257E21567

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

7073961, Jul 11, 2006

Feb 1, 2005

11/050073

William Paul Mazotti - San Martin CA, US
Jia Liu - San Jose CA, US
Luu Thanh Nguyen - San Jose CA, US
Haryanto Chandra - Sunnyvale CA, US
Peter Deane - Los Altos CA, US
Todd Thyes - Appleton WI, US
Brian Huss - Appleton WI, US
John Rukavina - Neenah WI, US
Glenn Woodhouse - Pullman WA, US

National Semiconductor Corporation - Santa Clara CA

G02B 6/36

385 94

Techniques for manufacturing an optical transmission device in a manner so that the photonic device is protected from damage that can be caused by exposure to the environment and physical handling are described. The invention involves placing a lens or a lens array over a photonic device, either with or without the use of a receptacle device, such that the photonic device is contained within a sealed cavity. The invention has three main embodiments in which the photonic device can be hermetically sealed, quasi-hermetically sealed, or non-hermetically sealed. The optical transmission device can be configured to serve as an optical receiver, detector, or a transceiver device.