LOREN THOMAS LANCASTER
Pilots at Los Reyes Cir, Colorado Springs, CO

6363011, Mar 26, 2002

Jul 25, 2000

09/626267

Ryan T. Hirose - Colorado Springs CO
Loren T. Lancaster - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

G11C 1604

36518507, 36518508, 36518905

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

6614070, Sep 2, 2003

Jul 10, 2000

09/613874

Ryan T. Hirose - Colorado Springs CO
Loren T. Lancaster - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

H01L 29788

257316, 257322, 257324, 257326, 365184

A NAND stack array ( ) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors ( ) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

6709928, Mar 23, 2004

Jul 31, 2001

09/920378

Fred Jenne - Los Gatos CA
Loren Thomas Lancaster - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

H01L 21336

438264, 438261, 438591, 438775, 438778, 438257

A semiconductor device and method of manufacturing a semiconductor device is disclosed in which a SONOS-type dielectric may include a charge storing dielectric (206) that includes at least one charge trapping dielectric layer (212) formed within. A charge trapping dielectric layer (212) may be a silicon-rich silicon nitride layer that may trap charge that could otherwise tunnel through a charge storing dielectric (206). A method may include forming a tunneling dielectric (302), forming a first portion of a charge storing layer (304-0), forming a charge trapping layer (306), forming a second portion of a charge storing layer (304-1), and forming a top dielectric (308).

5760644, Jun 2, 1998

Oct 25, 1996

8/735973

Loren T. Lancaster - Colorado Springs CO
Ryan T. Hirose - Colorado Springs CO

NVX Corporation - Colorado Springs CO

H01L 2500

327566

A semiconductor integrated circuit to determine a passage of time that may include a time during which no electrical power is supplied to the circuit is disclosed. The circuit has a timing device that includes a memory storage dielectric material for trapping charge carriers and releasing the trapped charge carriers in a known manner over time. The timing device has an electrical parameter that is relatable to an electric field created by the trapped charge carriers. A charge injection circuit is provided for selectively injecting charge carriers into the memory storage dielectric material to create an initialized state, and a time reader circuit determines when the electrical parameter has reached a predetermined value that corresponds to a passage of a predetermined time. Preferably the timing device is an insulated gate field effect transistor in which the memory storage dielectric material is a dielectric material, such as SONOS or SNOS, between the gate and channel overlying at least the channel area.

6140676, Oct 31, 2000

May 20, 1998

9/082167

Loren T. Lancaster - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

H01L 2978, H01L 3300

257315

A non-volatile memory IGFET device has a gate dielectric stack that is dielectrically equivalent to a layer of silicon dioxide having a thickness of 170. ANG. or less. Above the dielectric stack is a polycrystalline silicon gate that is doped in an opposite manner to that of the source and drain regions of the transistor. By using a gate doping that is opposite to that of the IGFET source and drain regions, the poly depletion layer that can occur during programming in modern and advanced memory devices is eliminated according to this invention. The device of this invention forms an accumulation layer in the poly rather than a depletion layer. This difference not only greatly improves the program speed, but allows for selecting the gate doping at levels as low as 10. sup. 11 /cm. sup. 3, or less, without significantly compromising the program speed. Further, since the majority of the applied voltage in a device according to this invention is dropped over the gate dielectric, rather than shared between the gate dielectric and a depletion layer in the gate poly, the device of this invention can be scaled in gate dielectric thickness without significantly compromising the program speed.

6122191, Sep 19, 2000

Aug 19, 1998

9/136694

Ryan T. Hirose - Colorado Springs CO
Loren T. Lancaster - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

G11C 1604

36518501

A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

5656837, Aug 12, 1997

Apr 16, 1996

8/633857

Loren T. Lancaster - Colorado Springs CO
Ryan T. Hirose - Colorado Springs CO

NVX Corporation - Colorado Springs CO

H01L 27115

257314

A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151,. . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).

5510638, Apr 23, 1996

Apr 28, 1994

8/234288

Loren T. Lancaster - Colorado Springs CO
Ryan T. Hirose - Colorado Springs CO

NVX Corporation - Colorado Springs CO

H01L 27115

257314

A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151,. . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).

6163048, Dec 19, 2000

Apr 16, 1998

9/051700

Ryan T. Hirose - Colorado Springs CO
Loren T. Lancaster - Colorado Springs CO

Cypress Semiconductor Corporation - San Jose CA

H01L 29788, G11C 1604

257315

A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

5789776, Aug 4, 1998

Sep 18, 1996

8/715569

Loren T. Lancaster - Colorado Springs CO
Ryan T. Hirose - Colorado Springs CO

NVX Corporation - Colorado Springs CO

H01L 27108, H01L 2976, H01L 2994, H01L 31119

257296

A non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.