LEE J JACOBSON
Electrician in Portland, ME
License number
Massachusetts 31774
Issued Date
Mar 28, 1988
Expiration Date
Jul 31, 1998
Type
Journeyman Electrician
Address
Address
Portland, ME 04107
Professional information
Staff Mems Device Yield Engineer At Analog Devices
Position:
Staff MEMS Device Yield Engineer at Analog Devices, Staff Device Yield Engineer at Analog Devices, Micromachined Products Division
Location:
Portland, Maine Area
Industry:
Semiconductors
Work:
Analog Devices
-
Staff MEMS Device Yield Engineer
Analog Devices, Micromachined Products Division
since 2007
-
Staff Device Yield Engineer
National Semiconductor
1995 - 2007
-
Development Engineer
National Semiconductor
1995 - 2006
-
Staff Advanced Process Development Engineer
Education:
University of Southern Maine
Structure For Decreasing Minimum Feature Size In An Integrated Circuit
US Patent:
2007005, Mar 8, 2007
Filed:
Nov 3, 2006
Appl. No.:
11/592800
Inventors:
Andre Labonte - Lewiston ME, US
Lee Jacobson - Cape Elizabeth ME, US
Lee Jacobson - Cape Elizabeth ME, US
International Classification:
H01L 29/00, C25F 3/00
US Classification:
257499000, 216011000
Abstract:
A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.
System And Method For Providing A Cmos Compatible Single Poly Eeprom With An Nmos Program Transistor
US Patent:
7447064, Nov 4, 2008
Filed:
Mar 27, 2006
Appl. No.:
11/389984
Inventors:
Jiankang Bu - Windham ME, US
Lee Jacobson - Cape Elizabeth ME, US
David Courtney Parker - Topsham ME, US
Lee Jacobson - Cape Elizabeth ME, US
David Courtney Parker - Topsham ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G11C 11/34
US Classification:
36518501, 36518518, 36518505, 257315
Abstract:
A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.
System And Method For Providing Contact Etch Selectivity Using Rie Lag Dependence On Contact Aspect Ratio
US Patent:
7504340, Mar 17, 2009
Filed:
Jun 14, 2004
Appl. No.:
10/866914
Inventors:
Sergei Drizlikh - Scarborough ME, US
Thomas John Francis - South Portland ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Thomas John Francis - South Portland ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/302
US Classification:
438700, 438712, 438714, 438743, 216 59
Abstract:
A system and method is disclosed for providing contact etch selectivity for the etching of a plurality of contact etch holes through a dielectric layer of an integrated circuit. The method comprises the steps of obtaining a value of the reactive ion etch (RIE) lag for the dielectric layer, and selecting different values for the diameters of the contact etch holes based upon the desired depths of the contact etch holes and on the value of the RIE lag for the dielectric layer. The invention also comprises a contact diameter application processor that is capable of using RIE lag data to calculate contact diameters for contact etch holes for a mask design layout of an integrated circuit.
System And Method For Providing Low Voltage High Density Multi-Bit Storage Flash Memory
US Patent:
8004032, Aug 23, 2011
Filed:
May 19, 2006
Appl. No.:
11/437564
Inventors:
Jiankang Bu - Windham ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Andre Paul Labonte - Lewiston ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Andre Paul Labonte - Lewiston ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 29/788
US Classification:
257315, 257317, 257E293
Abstract:
A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.
System And Method For Providing Low Voltage High Density Multi-Bit Storage Flash Memory
US Patent:
8241975, Aug 14, 2012
Filed:
Aug 4, 2011
Appl. No.:
13/198507
Inventors:
Jiankang Bu - Windham ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Andre Paul Labonte - Lewiston ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Andre Paul Labonte - Lewiston ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/8238
US Classification:
438211, 438279, 438283, 257E21422
Abstract:
A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.
System And Method For Providing Testing And Failure Analysis Of Integrated Circuit Memory Devices
US Patent:
7216270, May 8, 2007
Filed:
May 14, 2004
Appl. No.:
10/846004
Inventors:
Lee James Jacobson - Cape Elizabeth ME, US
Todd Wayne Karry - Kennebunk ME, US
Todd Wayne Karry - Kennebunk ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G11C 29/54, G11C 29/02
US Classification:
714718, 714763
Abstract:
A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that is due to presence of the physical fault in the test circuit. The electrical signatures from the test circuits are compared with a signal from an integrated circuit memory device to determine whether any of the physical faults in the test circuits are present in the integrated circuit memory device.
System And Method For Providing Testing And Failure Analysis Of Integrated Circuit Memory Devices
US Patent:
7484143, Jan 27, 2009
Filed:
May 7, 2007
Appl. No.:
11/800656
Inventors:
Lee James Jacobson - Cape Elizabeth ME, US
Todd Wayne Karry - Kennebunk ME, US
Todd Wayne Karry - Kennebunk ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G11C 29/44, G11C 29/50
US Classification:
714718, 714724
Abstract:
A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that is due to presence of the physical fault in the test circuit. The electrical signatures from the test circuits are compared with a signal from an integrated circuit memory device to determine whether any of the physical faults in the test circuits are present in the integrated circuit memory device.
Method For Forming A Lens Using Sub-Micron Horizontal Tip Feature
US Patent:
7858428, Dec 28, 2010
Filed:
Jul 11, 2005
Appl. No.:
11/179059
Inventors:
Lee James Jacobson - Cape Elizabeth ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438 65, 438 57, 438 64
Abstract:
A method for creating graded or tapered dopant profiles in a semiconductor layer or layers. Preferably, a sub-micron horizontal tip feature is used to control the doping of the layer beneath the feature.
Method Of Forming A Sub-Micron Tip Feature
US Patent:
7175777, Feb 13, 2007
Filed:
Dec 2, 2003
Appl. No.:
10/726122
Inventors:
André Paul Labonté - Lewiston ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Lee James Jacobson - Cape Elizabeth ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G01L 21/30
US Classification:
216 59, 216 26, 438689, 438700, 438712, 438713, 438696, 438706, 438725, 430302, 430312, 430313, 430314
Abstract:
A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.