LEE BOEKELHEIDE
Pilots at Ann Pl, Portland, OR
License number
Oregon A0171850
Issued Date
Apr 2015
Expiration Date
Apr 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
12180 SW Ann Pl, Portland, OR 97223
Personal information
See more information about LEE BOEKELHEIDE at radaris.comName
Address
Phone
Beaverton, OR
12180 Ann Pl, Portland, OR 97223
12180 Ann St, Tigard, OR 97223
Professional information
See more information about LEE BOEKELHEIDE at trustoria.com
Vp Mm At Providenza &Amp; Boekelheide, Inc.
Vp Mm At Providenza &Amp; Boekelheide, Inc.
Position:
VP MM at Providenza & Boekelheide, Inc.
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Providenza & Boekelheide, Inc.
since Jan 1994
-
VP MM
NXP Semiconductors
1994 - 2009
-
Consultant
Graphic Software Systems
1982 - 1992
-
Fellow
Tektronix
1975 - 1981
-
Engineer
Education:
Portland State University 1969 - 1976
B.S., Mathematics
B.S., Mathematics
Interests:
Architecture, design and implementation of complex hardware, software and firmware systems
airplanes
Image Processor Memory For Expediting Memory Operations
Image Processor Memory For Expediting Memory Operations
US Patent:
5345555, Sep 6, 1994
Filed:
Jun 14, 1993
Appl. No.:
8/077705
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G06F 1562
US Classification:
395164
Abstract:
An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.
Bit Aligned Data Block Transfer Method And Apparatus
Bit Aligned Data Block Transfer Method And Apparatus
US Patent:
5313576, May 17, 1994
Filed:
Nov 23, 1990
Appl. No.:
7/617198
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G06F 1562
US Classification:
395164
Abstract:
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.
Bit Aligned Data Block Transfer Method And Apparatus
Bit Aligned Data Block Transfer Method And Apparatus
US Patent:
5347631, Sep 13, 1994
Filed:
Oct 12, 1993
Appl. No.:
8/135797
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G06F 1562
US Classification:
395164
Abstract:
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.
Image Processor Memory For Expediting Memory Operations
Image Processor Memory For Expediting Memory Operations
US Patent:
5487051, Jan 23, 1996
Filed:
Mar 18, 1994
Appl. No.:
8/210355
Inventors:
John R. Providenza - Beaverton OR
Lee Boekelheide - Tigard OR
Lee Boekelheide - Tigard OR
Assignee:
Network Computing Devices, Inc. - Mountain View CA
International Classification:
G11C 1300
US Classification:
365233
Abstract:
An electronic data storage memory performs logic operations on the data values existing in its storage cells to eliminate the number of necessary memory accesses during bitblts. The time in which a bitblt can be completed in an image processing system is prolonged because of the number of memory cycles performed during a "raster operation". Thus, to reduce the number of necessary memory cycles, simple logic operations are performed in image processor memory so that a raster operation may take place without having to read, for example, the destination operand from memory. Since a bitblt performs a raster operation on each pixel in the bitblt block, the reduction in memory access time is proportional to the size of the bitblt block.