LAWRENCE STEVAN UZELAC
Pilots at Bar Rnch Rd, Auburn, CA
License number
California A1950147
Issued Date
Feb 2017
Expiration Date
Aug 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
10444 Bar Ranch Rd, Auburn, CA 95603
Professional information
Temperature Compensated Output Driver
US Patent:
6650170, Nov 18, 2003
Filed:
Sep 27, 2002
Appl. No.:
10/259080
Inventors:
Lawrence S. Uzelac - Auburn CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 3500
US Classification:
327513, 327112
Abstract:
According to some embodiments, a drive circuit provides an output resistance substantially stable despite variations in operating temperature.
Power-Up Logic Reference Circuit And Related Method
US Patent:
6617874, Sep 9, 2003
Filed:
Jan 2, 2002
Appl. No.:
10/038196
Inventors:
Lawrence S. Uzelac - Auburn CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19173
US Classification:
326 38, 326 31, 326 46
Abstract:
A power-up reference circuit and related method that generates a reference voltage in response to the circuit being powered up. The circuit includes a power-up sensing circuit that generates a set signal, a latch to generate and sustain the reference voltage in response to the set signal, and a reset key decoder to receive an N-bit key and in response thereto generate a reset signal that causes the latch to reset. Upon the circuit being powered up, the power-up sensing circuit generates the set signal which sets the latch to generate the reference voltage. The reference voltage can be used by other circuits to initialize their operating conditions. Once the reference voltage has been used, the N-bit key is generated which causes the decoder to generate the reset signal, which in turn, causes the latch to reset. When the latch is reset, the power-up reference circuit consumes substantially no power.
Circuit In Which The Time Delay Of An Input Clock Signal Is Dependent Only On Its Logic Phase Width And A Ratio Of Capacitances
US Patent:
6834355, Dec 21, 2004
Filed:
Dec 15, 2000
Appl. No.:
09/738695
Inventors:
Lawrence S. Uzelac - Auburn CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 104
US Classification:
713401, 713400
Abstract:
The invention provides, in an embodiment, a structure, method and means for generating clock phases, synchronized to the system clock, that to first order are independent of process parameters including drive current, parasitic resistance and parasitic capacitance. In one aspect, an apparatus is provided to generate an output phase at a predetermined time relative to an input clock signal and dependent on a logic phase width of the input clock signal. In another aspect, the apparatus includes similar circuit components with unequal units, the predetermined time is further dependent on the units ratio of the similar circuit components. In another aspect, the apparatus is cascaded with at least one reproduction of the apparatus, and configured to provide a multiple of the input clock signal. In another aspect, the apparatus is coupled in parallel with at least one reproduction of the apparatus, and configured to provide at least two output phases generated in parallel during the input clock signal.
Method And Apparatus For Changing Bias Levels To Reduce Cmos Leakage Of A Real Time Clock When Switching To A Battery Mode Of Operation
US Patent:
6611918, Aug 26, 2003
Filed:
Dec 21, 1999
Appl. No.:
09/469986
Inventors:
Lawrence S. Uzelac - Auburn CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 132
US Classification:
713320, 713300, 713323
Abstract:
A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.
Method And Apparatus For Minimizing Leakage Current In Semiconductor Logic
US Patent:
7406609, Jul 29, 2008
Filed:
Sep 8, 2005
Appl. No.:
11/221694
Inventors:
Lawrence S. Uzelac - Auburn CA, US
Andrew M. Volk - Granite Bay CA, US
Andrew M. Volk - Granite Bay CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00, G06F 1/26
US Classification:
713300, 713320
Abstract:
Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.
Method And Apparatus For Reducing Sub-Threshold Off Current For A Real Time Clock Circuit During Battery Operation
US Patent:
2004005, Mar 18, 2004
Filed:
Jul 22, 2003
Appl. No.:
10/625584
Inventors:
Lawrence Uzelac - Auburn CA, US
Andrew Volk - Granite Bay CA, US
Andrew Volk - Granite Bay CA, US
Assignee:
Intel Corporation, a California corporation
International Classification:
G06F001/32
US Classification:
713/320000
Abstract:
A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.