LARRY G JONES
Electrician at Whitsun Dr, Austin, TX

5619418, Apr 8, 1997

Feb 16, 1995

8/390210

David T. Blaauw - Austin TX
Joseph W. Norton - Austin TX
Larry G. Jones - Austin TX
Susanta Misra - Bangalore, IN
R. Iris Bahar - Boulder CO

Motorola, Inc. - Schaumburg IL

G06F 1750

364489

An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing logic gates from a memory stored logic gate library. A circuit representation is read along with timing constraints for circuit paths. Each circuit path in the circuit is processed to find it's actual circuit path delay. A most out-of-specification circuit path (in terms of speed) is chosen in the circuit and a sensitivity calculation is performed for each logic gate in the most out-of-specification circuit path. The logic gate in the circuit path with the maximized sensitivity (sensitivity=. DELTA. speed/. DELTA. area) is increased in size by accessing a larger gate in the library in order to improve speed at the expense of area.

5689432, Nov 18, 1997

Jan 17, 1995

8/373695

David T. Blaauw - Austin TX
Robert L. Maziasz - Austin TX
Joseph W. Norton - Austin TX
Larry G. Jones - Austin TX
Mohankumar Guruswamy - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1750

364490

A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.

5790416, Aug 4, 1998

Sep 18, 1995

8/529772

Joseph Wayne Norton - Austin TX
David Theodore Blaauw - Austin TX
Larry Grant Jones - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2170, H01L 2350

364490

A process and implementing computer system (13) for updating circuit representations in a hierarchical Directed Acyclic Graph (DAG) format (400-410) based upon changes made to the primitive components of the circuit in a flat representation (201-213) includes performing a depth first search (505) on the hierarchical representation of the circuit beginning at the root level (501) for a given path. At each lower level, each child instance is visited (505) and if there is any change in any attribute between the hierarchical and flat representations (509), the component in the hierarchical representation which needs to be changed is copied (807) and connected to the children components of the original hierarchical representation. Changes in the attributes of the children components are made in the copied component (809). If the new component already exists in the hierarchy 811, then that component is deleted (817), otherwise the copied component is returned (813), and changes are passed upwardly to the root level (815) where the previous DAG may be replaced with the copied and updated DAG which includes changes in the attributes of components of a corresponding flat circuit representation.

5737236, Apr 7, 1998

Feb 8, 1996

8/598555

Robert Maziasz - Austin TX
Mohankumar Guruswamy - Austin TX
Daniel W. Dulitz - Austin TX
David Blaauw - Austin TX
Larry Jones - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1750

364490

The present invention relates to a method (100, 150, 200) and associated data processing system (250) for determining a standard cell height within an integrated circuit design. A plurality of cell types, each cell type including a plurality of cell structures are received (102). Then, weighting values are received, one for each cell type (104). Expected intercell connection densities are preferably also received. Various target cell heights are processed with the plurality of cell types, the weighting values, and the expected intercell connection densities to generate a standard cell height (106). The standard cell height used with the integrated circuit design produces an optimized integrated circuit area, preferably a minimum area. The present invention includes a method (200) and system (250) for selecting an optimized standard cell height that, when used with a place-and-route tool to generate a physical design file (204) produces an optimized physical integrated circuit design. A method of manufacture (300) is also included.

5666288, Sep 9, 1997

Apr 21, 1995

8/426211

Larry G. Jones - Austin TX
David T. Blaauw - Austin TX
Robert L. Maziasz - Austin TX
Mohan Guruswamy - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1750

364490

A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing individual transistor sizes, power rail sizes, cell pitch, and the like in a step (103). Once the optimization has occurred, the initial library can no longer be used to place and route the IC. Therefore, a hybrid logic cell library is created from the gate schematic netlist (102) via a step (105). This hybrid library and the above optimizations provides a placed and routed IC via a step (126) in a short design cycle while optimizing performance of the IC.