KRISHNAN SRINIVASAN
Pilots at Johnson Ave, San Jose, CA
License number
California C1045424
Issued Date
Feb 2016
Expiration Date
Feb 2018
Category
Airmen
Address
Address
1400 Johnson Ave, San Jose, CA 95129
Professional information
Apparatus And Methods For On Layer Concurrency In An Integrated Circuit
US Patent:
8438306, May 7, 2013
Filed:
Nov 2, 2010
Appl. No.:
12/938120
Inventors:
Benoit De Lescure - La Colle-sur-Loup, FR
Krishnan Srinivasan - San Jose CA, US
Krishnan Srinivasan - San Jose CA, US
Assignee:
Sonics, Inc. - Milpitas CA
International Classification:
G06F 13/00
US Classification:
709238, 709249, 709250
Abstract:
A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.
Apparatus And Methods To Concurrently Perform Per-Thread As Well As Per-Tag Memory Access Scheduling Within A Thread And Across Two Or More Threads
US Patent:
2012003, Feb 9, 2012
Filed:
Aug 6, 2010
Appl. No.:
12/852355
Inventors:
KRISHNAN SRINIVASAN - SAN JOSE CA, US
RUBEN KHAZHAKYAN - YEREVAN, AM
HARUTYUN ASLANYAN - YEREVAN, AM
DREW E. WINGARD - PALO ALTO CA, US
CHIEN-CHUN CHOU - SARATOGA CA, US
RUBEN KHAZHAKYAN - YEREVAN, AM
HARUTYUN ASLANYAN - YEREVAN, AM
DREW E. WINGARD - PALO ALTO CA, US
CHIEN-CHUN CHOU - SARATOGA CA, US
Assignee:
SONICS, INC - MILPITAS CA
International Classification:
G06F 9/46, G06F 12/14, G06F 1/12, G06F 12/00
US Classification:
718102, 711163, 711105, 713400, 711E12001, 711E12093
Abstract:
A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.