KIRUBAKARAN PERIYANNAN
Pilots at Marquette St, Santa Clara, CA
License number
California A4435575
Issued Date
Jan 2016
Expiration Date
Jan 2021
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
3570 Marquette St, Santa Clara, CA 95051
Professional information
Spi Nand Protected Mode Entry Methodology
US Patent:
2009027, Nov 5, 2009
Filed:
Apr 30, 2008
Appl. No.:
12/112880
Inventors:
Theodore T. Pekny - Sunnyvale CA, US
Samuel A. Shapero - San Jose CA, US
Kirubakaran Periyannan - Santa Clara CA, US
Samuel A. Shapero - San Jose CA, US
Kirubakaran Periyannan - Santa Clara CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 12/02, G06F 12/14
US Classification:
711103, 711164, 711E12008, 711E12094
Abstract:
One or more techniques are provided for restricting access to protected modes of operation in a memory device. In one embodiment, detection circuitry is provided and configured to receive and evaluate a protected mode entry sequence for accessing a protected mode of operation. The detection circuitry may be further configured to temporarily enable an output pin on a serial interface between the memory device and a master device to receive inputs, such that a entry sequence may be entered on both the input and output pins. In another embodiment, the detection circuitry may be enabled only if a security code is first provided, thus requiring both the correct security code and entry sequence before protected mode access is allowed. The memory device may also include a parallel NAND memory array, and detection logic may be further configured to enable a serial-to-parallel NAND translator once protected mode access is allowed.
Protecting Groups Of Memory Cells In A Memory Device
US Patent:
8645616, Feb 4, 2014
Filed:
Feb 3, 2011
Appl. No.:
13/020517
Inventors:
Kirubakaran Periyannan - Santa Clara CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 12/00
US Classification:
711103, 711163, 711E12008
Abstract:
Methods for memory block protection and memory devices are disclosed. One such method for memory block protection includes programming protection data to protection bytes diagonally across different word lines of a particular memory block (e. g. , Boot ROM). The protection data can be retrieved by an erase verify operation that can be performed at power-up of the memory device.