DR. KHANH CONG TRAN, MD
Medical Practice at Senter Rd, San Jose, CA

6329718, Dec 11, 2001

Jun 26, 1998

9/105775

Minh Van Ngo - Union City CA
Paul R. Besser - Sunnyvale CA
Matthew Buynoski - Palo Alto CA
John Caffall - San Carlos CA
Nick MacCrae - San Jose CA
Richard J. Huang - Cupertino CA
Khanh Tran - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2348, H01L 2352

257765

A method for making 0. 25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

6133142, Oct 17, 2000

Dec 18, 1997

8/992628

Khanh Tran - San Jose CA
Jeff Shields - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438625

Reliable vias are formed by providing an adequate landing area without increasing the size of the underlying feature. Embodiments include forming a lower metal feature with an ARC layer extending beyond the side surfaces of the primary conductive portion serving as an etch stop when forming the through-hole. The overhanging portion provides a suitable landing pad without increasing the size of the underlying feature. Embodiments include ARCs having a thickness ranging from about 1000. ANG. to about 1300. ANG. and an overhanging portion extending beyond the side surface of the primary conductive portion up to about 0. 05 microns.

6008116, Dec 28, 1999

Dec 18, 1997

8/993120

Khanh Tran - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21469

438623

Planarization of a dielectric interlayer containing a dielectric gap filled layer is improved and facilitated by selective etching to reduce or eliminate steps in the gap filled dielectric layer before oxide deposition and polishing. Embodiments include gap filling a patterned metal layer with SOG or HSQ, forming a photoresist mask with an opening over steps having a height greater than about 3,000. ANG. , etching to reduce the height of the step by at least 70% depositing silicon oxide derived from TEOS or silane by PECVD and CMP.

2012032, Dec 27, 2012

Jun 24, 2011

13/168632

Loc T. Pham - San Jose CA, US
Omar Alonso Macy - San Jose CA, US
Khanh Tran - San Jose CA, US

Real Action Paintball, Inc. a California Corporation - San Jose CA

F41B 11/02, F41B 11/00

124 73, 124 83, 124 45, 102502

A paintball assembly capable of retaining a paintball in a loading chamber using a paintball catcher is disclosed. The paintball assembly includes a loading chamber, a detent, and a bolt. The loading chamber is coupled to a loading port to receive paintballs. In one embodiment, the detent includes a paintball catcher capable of catching the paintball as it is loaded into the loading chamber. In one example, the paintball catcher is a flexible paintball catcher extending into the loading chamber and is able to catch the paintball and hold it in a predefined position. When a trigger is pulled, the bolt pushes the paintball into a firing chamber while the paintball catcher releases the paintball.

6046106, Apr 4, 2000

Sep 5, 1997

8/924133

Khanh Q. Tran - San Jose CA
Paul R. Besser - Cupertino CA
Guarionex Morales - Santa Clara CA
Shekhar Pramanick - Fremont CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2144

438660

Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.

5866945, Feb 2, 1999

Oct 16, 1997

8/951592

Robert C. Chen - Los Altos CA
Jeffrey A. Shields - Sunnyvale CA
Robert Dawson - Austin TX
Khanh Tran - San Jose CA

Advanced Micro Devices - Sunnyvale CA

H01L 2348, H01L 2352

257750

Spin-on HSQ is employed to gap fill metal layers in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of borderless vias, as from photoresist stripping using an O. sub. 2 -containing plasma, is overcome by treating the degraded HSQ layer with an H. sub. 2 -containing plasma to restore the dangling Si--H bonds, thereby passivating the surface and preventing moisture absorption, before filling the via opening with conductive material, such as a barrier layer.

6087724, Jul 11, 2000

May 27, 1998

9/084737

Jeffrey A. Shields - Sunnyvale CA
Khanh Tran - San Jose CA
Robert Chen - Los Altos CA
Robert Dawson - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2348, H01L 2352, H01L 2940

257734

HSQ is employed for gap filling patterned metal layers. The surface of the deposited HSQ gap fill layer is modified to decrease its plasma etching rate. Embodiments include modifying the HSQ surface by exposure to a plasma, such as a nitrogen-containing plasma, e. g. , a plasma containing ammonia or hydrogen/nitrogen, to form a nitrided surface region. Reduction of the plasma etching rate of HSQ enables formation of reliable low resistance borderless vias.