Kent L Smith
Accountancy in Salt Lake City, UT

4583012, Apr 15, 1986

Oct 20, 1983

6/543956

Kent F. Smith - Salt Lake City UT
Tony M. Carter - Salt Lake City UT

General Instrument Corporation - New York NY

H03K 19177, H03K 19096, H03K 1920, G06F 748

307465

A logical circuit array is provided in which the AND and OR planes are folded together and all of the logic cell transistor gates are oriented in the same direction. The array comprises a plurality of AND rows R. sub. 0 through R. sub. n, and means for precharging the AND rows to one logic level, e. g. V. sub. DD. An additional row R. sub. a is provided along with means for precharging the additional row to another logic level, e. g. , ground. The array includes a plurality of data columns and an output column coupled to AND row R. sub. A plurality of logic cells is divided among AND rows R. sub. 0 through R. sub. n-1. Each of the logic cells has an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array. A plurality of logic cells is associated with AND row R. sub. n, with each such cell having an input terminal coupled to a data column, a first output terminal connected to AND row R. sub.

7733254, Jun 8, 2010

Jun 26, 2008

12/147254

Kent F. Smith - Holladay UT, US
Daniel J. Black - Draper UT, US
Steve R. Jacobs - Salt Lake City UT, US

Slicex, Inc. - Sandy UT

H03M 1/38, H03M 1/00

341135, 341155, 341156, 341161

A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.

4297598, Oct 27, 1981

Apr 5, 1979

6/027507

Kent F. Smith - Salt Lake City UT

General Instrument Corporation - Clifton NJ

H03K 524, G11C 700

307355

An I. sup. 2 L circuit is provided for sensing relatively small differences in magnitude between two input signals. A dual input bistable circuit generates an output representative of the degree to which each of the bistable circuit inputs is actuated, subsequent to the energization of the bistable circuit by a current source in the form of an injector transistor, which is disabled to reset the bistable circuit. A pair of load transistors are provided, the control terminals of which are, respectively, connected to receive the input signals. Each load transistor serves to actuate a different one of the bistable means inputs to a degree dependent upon the conductivity thereof, which, in turn, is dependent upon the magnitude of the input signal connected thereto. The load transistors also serve to isolate the source of the input signals from the energizing injector current, to prevent the sensing circuit from disrupting the state of the source of the input signals.

2006024, Nov 2, 2006

May 1, 2006

11/415608

Kent Smith - Holladay UT, US
Tracy Johancsik - Murray UT, US

H03K 19/003

326027000

Systems for reducing ringing of a signal generated by a digital signal source circuit include a number of driver circuits configured to incrementally increase an output impedance of the source circuit. The increase in output impedance is configured to reduce the ringing of the signal. Methods of reducing ringing of a signal generated by a digital signal source circuit include incrementally increasing an output impedance of the source circuit. The increase in output impedance is configured to reduce the ringing of the signal.

4417327, Nov 22, 1983

Sep 9, 1980

6/185538

Kent F. Smith - Salt Lake City UT

G11C 1300

365203

A clocked structured logic array functions in a dynamic, rather than static, mode of operation. The column output conductors and row conductors of the array are precharged to a predetermined voltage level at the beginning of a clock cycle. At the termination of a first phase of the clock cycle, the column conductors are selectively discharged in accordance with information stored in column memory elements. Upon termination of a second phase of the clock cycle, the row conductors are selectively discharged in accordance with a predetermined program, and responsive to the states of the column output conductors. The states of the row conductors are selectively transmitted to the column input conductors, and during a third phase of the clock cycle the information related to the states of the input conductors is transmitted to the memory elements.

4193126, Mar 11, 1980

Dec 4, 1978

5/966020

Kent F. Smith - Salt Lake City UT

General Instrument Corporation - Clifton NJ

G11C 1140

365174

The memory unit comprises a plurality of bipolar inverter transistors and an equal number of injector transistors, each of which acts as a current source for a different one of the inverter transistors. Means are provided for cross-coupling a first and a second of the inverter transistors to form a flip-flop. Third, fourth and fifth inverter transistors provide input data flow from the data line to the cross-coupled first and second inverters, in accordance with a write control sixth inverter transistor connected to receive a write signal. A seventh inverter transistor provides data output flow between the cross-coupled first and second inverter transistors and the data line in accordance with the read control eighth inverter transistor connected to receive a read signal.