KENNETH WAYNE SMITH, COTA/L
Occupational Therapy at Spring River Ct, Boise, ID

6055610, Apr 25, 2000

Aug 25, 1997

8/918209

Kenneth K. Smith - Boise ID
Loren P. Staley - Cool CA
Sorin Iacobovici - San Jose CA

Hewlett-Packard Company - Palo Alto CA

G06F 1200

711156

A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.

7023277, Apr 4, 2006

May 12, 2005

11/129115

Frederick Perner - Palo Alto CA, US
Kenneth Smith - Boise ID, US

Hewlett-Packard Development Company, L.P. - Houston TX

H03F 3/45

330261, 330257

The invention includes an apparatus and a method for minimizing power supply sensitivity of a differential amplifier. The apparatus includes a current source providing a differential amplifier bias current to a common source node of the differential amplifier. A voltage sensor senses variations of a power supply associated with the current source. Variations sensed by the voltage sensor control a magnitude of the differential amplifier bias current. The method includes a current source providing the source current. A voltage potential of the common source node is sensed. The current source is adjusted depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.

6842389, Jan 11, 2005

Jan 17, 2003

10/346700

Frederick A. Perner - Palo Alto CA, US
Kenneth K. Smith - Boise ID, US
Ken Eldredge - Boise ID, US
Lung Tran - Saratoga CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G11C 702, G11C 700

365209, 3652255

A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

2003018, Oct 9, 2003

Apr 9, 2002

10/120118

Sarah Brandenberger - Boise ID, US
Kenneth Smith - Boise ID, US
Kenneth Eldredge - Boise ID, US
Andrew Brocklin - Corvallis OR, US
Peter Fricke - Corvallis OR, US

G11C007/00

365/200000

A read-only memory device has multiple layers, where a first layer is formed on a semiconductor substrate, and one or more additional layers are formed over the first layer. Each layer has multiple non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component indicates a resistance value when a potential is applied to a selected memory cell. A memory component can be formed with a resistor, a resistor in series with a control element, or an anti-fuse device in series with a diode. A memory device having memory components that include an anti-fuse device can be programmed after manufacture, where an anti-fuse device indicates a high resistance value corresponding to a logical one when the memory device is manufactured, and indicates a low resistance value corresponding to a logical zero when a junction of the anti-fuse device is penetrated to form an electrical connection.

2012030, Dec 6, 2012

May 31, 2011

13/118964

Kurt Eugene Spears - Fort Collins CO, US
Kenneth K. Smith - Boise ID, US

H04N 9/73

3482271, 348E09051

An imaging system is disclosed. The imaging system has an image sensor and an illumination device. The imaging system captures two images, one with only ambient light, and the other with ambient light and light from the illumination device. The two images are synchronized such that the time between the start of the two image exposures is an integer multiple of at least one flicker period. The final image is created by subtracting the ambient only image from the other image.

6982909, Jan 3, 2006

Jan 27, 2004

10/765483

Frederick A. Perner - Palo Alt CA, US
Kenneth K. Smith - Boise ID, US
Corbin L. Champion - Pullman WA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G11C 7/00

36518907, 365148, 365158

A method of performing a read operation from a first magnetic random access memory (MRAM) cell in a memory cell string that includes the first MRAM cell coupled to a second MRAM cell. The method includes providing a voltage to a first end of the first memory cell string that is closest to the first MRAM cell, providing a ground source to a second end of the first memory cell string that is opposite the first end, and determining whether a voltage change occurred at a node between the first and second MRAM cells in response to applying a write sense current to the first MRAM cell.

7019381, Mar 28, 2006

Jul 1, 2003

10/611544

Kenneth K. Smith - Boise ID, US
Sarah M. Brandenberger - Boise ID, US
Judy Bloomquist, legal representative - Meridian ID, US
Kenneth J. Eldredge - Boise ID, US
Andrew L. Van Brocklin - Corvallis OR, US
Peter J. Fricke - Corvallis OR, US

Hewlett-Packard Development Company, L.P. - Houston TX

H01L 29/00

257536, 257528, 257537

A semiconductor substrate is provided over which electrically conductive columns are formed along with electrically conductive rows crossing over the electrically conductive columns. A plurality of memory components are formed each having a resistance value corresponding to multiple logical bits and non-volatile memory cells are each formed by connecting a memory component between an electrically conductive row and an electrically conductive column.

7221582, May 22, 2007

Aug 27, 2003

10/649078

Frederick A. Perner - Palo Alto CA, US
Kenneth K. Smith - Boise ID, US

Hewlett-Packard Development Company, L.P. - Houston TX

G11C 11/00

365158, 365171

Methods and apparatuses are disclosed for controlling the write current in magnetic memory. In some embodiments, the method includes: providing a current in a plurality of memory write lines (where the write lines may be magnetically coupled to at least one memory element), coupling a first and second plurality of transistors to either end of the memory write line, and altering the conduction state of individual transistors within the first and second plurality of transistors.

7290118, Oct 30, 2007

Jan 8, 2004

10/754663

Kenneth Kay Smith - Boise ID, US
Sarah Morris Brandenberger - Boise ID, US
Terrel Munden - Boise ID, US
Frederick A. Perner - Palo Alto CA, US
Connie Lemus - Boise ID, US
David McIntyre - Boise ID, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 12/00

711219, 711154, 36523004

A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The memory cells selected in parallel correspond to least significant bits of an address which has a range that includes the memory cells.

2005017, Aug 11, 2005

Feb 6, 2004

10/773708

Mauricio Alva - Boise ID, US
Kenneth Smith - Boise ID, US

G06F012/08

711104000, 711203000, 711105000, 711118000

A memory device comprises a magneto-resistive random access memory (MRAM), a cache comprising a volatile memory, and a decoder configured to translate referenced addresses to physical addresses to access data and pass the data between the MRAM and the cache and between the cache and a controller.