DR. KENNETH EGBERT WILLIAMS, M.D
Osteopathic Medicine at Preston Rd, Dallas, TX

4864543, Sep 5, 1989

Apr 30, 1987

7/045010

Morris D. Ward - Garland TX
Kenneth L. Williams - Dallas TX

Texas Instruments Incorporated - Dallas TX

G11C 700, G11C 1900

365221

A first-in, first-out memory has a write pointer (34) that includes a higher-order ring counter (192) and a lower-order ring counter (190). Ring counters (190, 192) store respective higher-order and lower-order address digits that are together used to select one of a plurality of write select gates (202). Each gate (202) is operable to both power up and address is coupled to a respective memory word location. A read pointer (28) of the FIFO has an analogous architecture. The lower-order and higher-order address digits generated by the write and read pointers (34 and 28) are used by a pointer comparator (44) to generate a plurality of intermediate signals. The intermediate signals are in turn received by a flag decoder (52) that generates EMPTY, FULL, ALMOST-FULL/EMPTY, and HALF-FULL status flags. A write-read control section (48) of the FIFO has a pair of monostable multivibrators (68, 82) that generate write and read clock pulses of a uniform pulse width. The write/read control (48) further has a disabling circuit that disables either the read clock monostable multivibrator (82) or the write clock monostable multivibrator (68) responsive to an equality signal (50) from the flag decoder (52) and responsive whether the last pulse was a write clock or a read clock.

5097442, Mar 17, 1992

Jan 21, 1988

7/146526

M. Dwayne Ward - Garland TX
Kenneth L. Williams - Dallas TX

Texas Instruments Incorporated - Dallas TX

G11C 700, G11C 1900

365 78

A first-in, first-out memory (10) can store a programmable number of data words at respective address locations within a memory (76). A read address generator (50, 58) generates a read pointer for pointing to a read address location in the memory (76). A depth address generator (42) points to a depth address location in the memory that is displaced from the read address location by a predetermined number of address locations. This depth address generator (42) is incremented to a next read depth address responsive to a read pulse (20) issued from a read/write controller (12). A write address generator (80) points to a write address location within memory (76). A comparator (52) compares the value stored in the write address generator (42) to the read depth address location stored in depth address generator (42) and is operable to generate a FULL memory status flag (24) responsive to their equality. Preferably, the comparator (52) also compares the read address to the write address, and is operable to generate an EMPTY status flag (26) responsive to their equality.

4829475, May 9, 1989

Aug 1, 1986

6/892228

Morris D. Ward - Garland TX
Kenneth L. Williams - Dallas TX

Texas Instruments Incorporated - Dallas TX

G11C 700, G11C 800

365 78

A First-In First-Out (FIFO) shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A write address ring counter (32) is responsive to first transitions (164, 168) of a write pulses to increment to successive stages (32) therein. A plurality of latches (154) are each responsive to a second transition (166) to latch in a write address bit. The latches (154) are each enabled to write the address bit to a respective memory register (50) upon a successive first transition (168).