JUSTIN SCOTT LEGAKIS
Pilots at Ln Mesa Ter, Sunnyvale, CA
License number
California A4714383
Issued Date
Nov 2016
Expiration Date
Nov 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
963 La Mesa Ter UNIT A, Sunnyvale, CA 94086
Professional information
Subpicture Overlay Using Fragment Shader
US Patent:
7542042, Jun 2, 2009
Filed:
Nov 10, 2004
Appl. No.:
10/985575
Inventors:
Roger L. Allen - San Jose CA, US
Rui M. Bastos - Porto Alegre, BR
Karim M. Abdalla - Menlo Park CA, US
Justin S. Legakis - Sunnyvale CA, US
Rui M. Bastos - Porto Alegre, BR
Karim M. Abdalla - Menlo Park CA, US
Justin S. Legakis - Sunnyvale CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 1/20, G06F 15/80, G09G 5/377, G09G 5/397, G09G 5/00
US Classification:
345506, 345505, 345629
Abstract:
A new method of operating a fragment shader to produce complex video content comprised of a video image or images, such as from a DVD player, that overlays a fragment shader-processed background. Pixels are fragment shader-processed during one loop or set of loops through a texture processing stations to produce a fragment shader-processed background. Then, at least some of those pixels are merged with the video or images to produce complex video content. The resulting complex image is then made available for further processing.
Computing Tessellation Coordinates Using Dedicated Hardware
US Patent:
8599202, Dec 3, 2013
Filed:
Sep 29, 2008
Appl. No.:
12/240390
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Emmett M. Kilgariff - San Jose CA, US
Michael C. Shebanow - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Michael C. Shebanow - Saratoga CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 15/30
US Classification:
345423
Abstract:
A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.
Method For Rasterizing Non-Rectangular Tile Groups In A Raster Stage Of A Graphics Pipeline
US Patent:
2007029, Dec 27, 2007
Filed:
Jun 23, 2006
Appl. No.:
11/474161
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Franklin C. Crow - Portola Valley CA, US
John S. Montrym - Los Altos Hills CA, US
Douglas A. Voorhies - Menlo Park CA, US
Franklin C. Crow - Portola Valley CA, US
John S. Montrym - Los Altos Hills CA, US
Douglas A. Voorhies - Menlo Park CA, US
International Classification:
G06T 1/20
US Classification:
345506
Abstract:
In a raster stage of a graphics pipeline, a method for rasterizing non-rectangular tile groups. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level by generating a non-rectangular footprint comprising a set of pixels related to the graphics primitive. The graphics primitive is then rasterized at a second level by accessing the set of pixels and determining covered pixels out of the set of pixels. The raster stage subsequently outputs the covered pixels for rendering operations in a subsequent stage of the graphics processor.
Single Pass Tessellation
US Patent:
2010007, Apr 1, 2010
Filed:
Sep 29, 2008
Appl. No.:
12/240382
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Emmett M. Kilgariff - San Jose CA, US
Henry Packard Moreton - Woodside CA, US
Emmett M. Kilgariff - San Jose CA, US
Henry Packard Moreton - Woodside CA, US
International Classification:
G06T 17/20
US Classification:
345423
Abstract:
A system and method for performing tessellation in a single pass through a graphics processor divides the processing resources within the graphics processor into sets for performing different tessellation operations. Vertex data and tessellation parameters are routed directly from one processing resource to another instead of being stored in memory. Therefore, a surface patch description is provided to the graphics processor and tessellation is completed in a single uninterrupted pass through the graphics processor without storing intermediate data in memory.
Rendering Of Disjoint And Overlapping Blits
US Patent:
7508397, Mar 24, 2009
Filed:
Nov 10, 2004
Appl. No.:
10/985690
Inventors:
Steven E. Molnar - Chapel Hill NC, US
Justin Legakis - Sunnyvale CA, US
Justin Legakis - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G09G 5/36, G06T 1/20, G06F 12/00
US Classification:
345562, 345505, 345506, 345537, 345563, 345564, 711168, 711169
Abstract:
Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory corresponding to the image. The data operations include a first data operation involving a first read operation followed by a first write operation, and a second data operation involving a second read operation followed by a second write operation. After starting the first read operation, a determination is made whether data associated with the first data operation overlaps with data associated with the second data operation. If a data overlap occurs, the second read operation is started after the first write operation is completed, and if no data overlap occurs, the second read operation is started before the first write operation is completed.
Apparatus And Method For Selective Attribute Distribution To Parallel Processors
US Patent:
7522169, Apr 21, 2009
Filed:
Dec 13, 2005
Appl. No.:
11/300228
Inventors:
Lukito Muliadi - San Jose CA, US
Justin S. Legakis - Sunnyvale CA, US
Justin S. Legakis - Sunnyvale CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06T 1/20, G06F 15/16, G06F 15/80, G06F 9/46
US Classification:
345506, 345502, 345503, 345505, 345520, 345522, 718105
Abstract:
A graphics processing unit has a set of parallel processing units. A primitive pipeline delivers tiles of a primitive to selected processing units of the set of processing units. An attribute pipeline distributes attributes to the selected processing units when the end of the primitive is reached, while withholding attributes from the remaining processing units of the set of processing units.
Apparatus And Method For Performing Blit Operations Across Parallel Processors
US Patent:
8059128, Nov 15, 2011
Filed:
Apr 19, 2006
Appl. No.:
11/407464
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US
Lukito Muliadi - San Jose CA, US
Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US
Lukito Muliadi - San Jose CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 15/80, G06F 21/00
US Classification:
345505, 345530, 345543, 711168
Abstract:
A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.
Boundary Transition Region Stitching For Tessellation
US Patent:
8120607, Feb 21, 2012
Filed:
May 30, 2008
Appl. No.:
12/130684
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Henry Packard Moreton - Woodside CA, US
Henry Packard Moreton - Woodside CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 17/20, G06T 17/00
US Classification:
345423, 345428
Abstract:
A system and method for stitching a boundary transition region of a patch produces a graphics primitive topology for the boundary transition region of the patch. A first number of vertices is computed for an inside edge of the boundary transition region using a first tessellation level of detail (LOD) of the inside edge. A second number of vertices is computed for an outside edge of the boundary transition region using a second tessellation LOD of the outside edge. A portion of the first number of vertices and the second number of vertices are merged based on a stitching pattern to produce a set of vertices for the boundary transition region. The set of vertices is stitched to produce an ordered list representing the graphics primitive topology.
Distributed Tessellation Topology Generator
US Patent:
8169437, May 1, 2012
Filed:
Jul 9, 2008
Appl. No.:
12/170383
Inventors:
Justin S. Legakis - Sunnyvale CA, US
Subodh Kumar - New Delhi, IN
Subodh Kumar - New Delhi, IN
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06T 15/30
US Classification:
345423, 345505, 345428
Abstract:
A system and method for dividing three-dimensional patches into tasks for processing receives control points defining a three dimensional patch and determines if a number of vertices of the three dimensional patch is greater than a maximum value. When the number of vertices is not greater than the maximum value, the three dimensional patch is output as a single task. When the number of vertices is greater than the maximum value, the three dimensional patch is divided into multiple tasks that each include a number of vertices that is not greater than the maximum value and the multiple tasks are output.