JUNE SIUFONG LEE, M.D.
Medical Practice at Lundy Ave, San Jose, CA
License number
California A50043
Category
Medical Practice
Type
Pediatrics
Address
Address
2
1715 Lundy Ave SUITE 108-116, San Jose, CA 95131
2360 Harvard St, Palo Alto, CA 94306
2360 Harvard St, Palo Alto, CA 94306
Phone
(408) 573-9686
Personal information
See more information about JUNE SIUFONG LEE at radaris.comName
Address
Phone
4807 North Ave, Carmichael, CA 95608
460 Francisco St APT 201, San Francisco, CA 94133
4566 Everest Cir, Cypress, CA 90630
4552 Ladoga Ave, Lakewood, CA 90713
441 Chalda Way, Moraga, CA 94556
Professional information
See more information about JUNE SIUFONG LEE at trustoria.com
System And Memory For Sequential Multi-Plane Page Memory Operations
System And Memory For Sequential Multi-Plane Page Memory Operations
US Patent:
7580283, Aug 25, 2009
Filed:
Sep 21, 2007
Appl. No.:
11/903282
Inventors:
June Lee - San Jose CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518511, 36523003, 36518533, 36518505, 36518908
Abstract:
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.
Programming And/Or Erasing A Memory Device In Response To Its Program And/Or Erase History
Programming And/Or Erasing A Memory Device In Response To Its Program And/Or Erase History
US Patent:
7679961, Mar 16, 2010
Filed:
Apr 25, 2007
Appl. No.:
11/739732
Inventors:
June Lee - San Jose CA, US
Fred Jaffin - Gilroy CA, US
Fred Jaffin - Gilroy CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 16/04
US Classification:
36518519, 36518518, 36518533, 36518529
Abstract:
For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.
System And Memory For Sequential Multi-Plane Page Memory Operations
System And Memory For Sequential Multi-Plane Page Memory Operations
US Patent:
8050131, Nov 1, 2011
Filed:
Aug 3, 2009
Appl. No.:
12/534586
Inventors:
June Lee - San Jose CA, US
Assignee:
Round Rock Research, LLC - Mt. Kisco NY
International Classification:
G11C 8/00
US Classification:
36523003, 36523006, 36523009, 3652331, 365239, 36518904
Abstract:
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.
System And Memory For Sequential Multi-Plane Page Memory Operations
System And Memory For Sequential Multi-Plane Page Memory Operations
US Patent:
8289802, Oct 16, 2012
Filed:
Mar 18, 2011
Appl. No.:
13/051221
Inventors:
June Lee - San Jose CA, US
Assignee:
Round Rock Research, LLC - Mt. Kisco NY
International Classification:
G11C 8/00
US Classification:
36523003, 36523006, 36523009, 3652331, 365239, 36518904
Abstract:
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.
System And Memory For Sequential Multi-Plane Page Memory Operations
System And Memory For Sequential Multi-Plane Page Memory Operations
US Patent:
7280398, Oct 9, 2007
Filed:
Aug 31, 2006
Appl. No.:
11/514746
Inventors:
June Lee - San Jose CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518511, 36518533, 36518523, 36518505, 36523003
Abstract:
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.
Programming And/Or Erasing A Memory Device In Response To Its Program And/Or Erase History
Programming And/Or Erasing A Memory Device In Response To Its Program And/Or Erase History
US Patent:
8194458, Jun 5, 2012
Filed:
Mar 16, 2010
Appl. No.:
12/724790
Inventors:
June Lee - San Jose CA, US
Fred Jaffin, III - Gilroy CA, US
Fred Jaffin, III - Gilroy CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518519, 36518518, 36518533, 36518529
Abstract:
For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.
Selective Bit Line Precharging In Non Volatile Memory
Selective Bit Line Precharging In Non Volatile Memory
US Patent:
7539059, May 26, 2009
Filed:
Dec 29, 2006
Appl. No.:
11/618637
Inventors:
June Lee - San Jose CA, US
Daniel Elmhurst - Folsom CA, US
Daniel Elmhurst - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/34, G11C 7/00, G11C 16/06
US Classification:
36518521, 36518503, 36518518, 36518525, 365203
Abstract:
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.
Methods And Control Circuitry For Programming Memory Cells
Methods And Control Circuitry For Programming Memory Cells
US Patent:
8194450, Jun 5, 2012
Filed:
Jun 15, 2010
Appl. No.:
12/815979
Inventors:
June Lee - San Jose CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 16/00
US Classification:
36518503, 36518524
Abstract:
Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell. If it is desired to alter a second digit of the data value of the memory cell, the memory cell is shifted to a third data state if the memory cell is in the first data state and shifted to a fourth data state if the memory cell is in the second data state. The first, second, third and fourth data states correspond to respective non-overlapping ranges of threshold voltages. The threshold voltages corresponding to the fourth data state are greater than the threshold voltages corresponding to the third data state.
Systems, Methods And Devices For Limiting Current Consumption Upon Power-Up
Systems, Methods And Devices For Limiting Current Consumption Upon Power-Up
US Patent:
2011017, Jul 21, 2011
Filed:
Apr 1, 2011
Appl. No.:
13/078771
Inventors:
JUNE LEE - San Jose CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 1/32
US Classification:
713320
Abstract:
Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.
Asynchronous/Synchronous Interface
Asynchronous/Synchronous Interface
US Patent:
7920431, Apr 5, 2011
Filed:
Jun 2, 2008
Appl. No.:
12/131152
Inventors:
Dean K. Nobunaga - Cupertino CA, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US
June Lee - San Jose CA, US
Chih Liang Chen - Sunnyvale CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/22
US Classification:
36518914, 36518903, 36518916, 36518915, 36518917, 36518918, 36518919, 36523003, 36523005, 3652331, 36523319
Abstract:
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.