JOSHUA JOHNSON
Medical Practice at 1 St, Rochester, MN
License number
Minnesota 60781
Category
Medical Practice
Type
Orthopaedic Surgery
Address
Address
200 1St St SW, Rochester, MN 55905
Phone
(507) 284-2511
Professional information
Computer / Computer Storage Engineer
Location:
Rochester, Minnesota Area
Industry:
Computer Hardware
Work:
LSI Corporation
- Rochester, MN Oct 2007 - May 2012
-
Integration Engineer / Systems Engineer / Systems Architect
Agere Systems
Oct 2006 - Oct 2007
-
Integration Engineer
FTL Systems Inc.
- Rochester, MN Feb 2000 - Oct 2006
-
Sr. Engineer
Education:
Excelsior College 1998 - 2005
B.S. Computer Information Systems, Computer Science
B.S. Computer Information Systems, Computer Science
Joshua Johnson - Rochester, MN
Work:
Caribou Coffee
Assistant Store Manager Southside Dental Clinic
Registered Dental Assistant Herzing University
Registrar Assistant
Assistant Store Manager Southside Dental Clinic
Registered Dental Assistant Herzing University
Registrar Assistant
Education:
Herzing University
Dental Assistant Diploma
Dental Assistant Diploma
Esd Discharge Path On Chasis-Mounted Pcb Assembly
US Patent:
2013032, Dec 12, 2013
Filed:
Jun 8, 2012
Appl. No.:
13/492152
Inventors:
David Alan Savory - Schnecksville PA, US
Joshua A. Johnson - Rochester MN, US
Joshua A. Johnson - Rochester MN, US
International Classification:
H05K 5/00, G06F 1/16
US Classification:
36167933, 361753
Abstract:
In described embodiments, a printed circuit board assembly capable of discharging electro-static discharge (ESD) surges includes an isolation trench track provided in the printed circuit board in close proximity to the peripheral edges between the peripheral edges and the mounting area, and a discharge path formed of conductive material to ground provided between the isolation trench track and the peripheral edges. The discharge path includes the board mounting screws and connects to a power connector ground of the printed circuit board.
Joshua Brent Johnson, Rochester MN
Specialties:
Radiology, Diagnostic Radiology
Work:
Mayo Clinic
200 1St St Sw, Rochester, MN 55905 Mayo Clinic Health System AlbertLea
404 W Fountain St, Albert Lea, MN 56007
200 1St St Sw, Rochester, MN 55905 Mayo Clinic Health System AlbertLea
404 W Fountain St, Albert Lea, MN 56007
Dr. Joshua B Johnson, Rochester MN - MD (Doctor of Medicine)
Specialties:
Diagnostic Radiology
Age:
46
Address:
200 1St St SW, Rochester 55905
(507) 284-2511 (Phone)
(507) 284-2511 (Phone)
Languages:
English
Method For Accelerating Simulation Performance And Increasing Simulation Accuracy Of Models Using Dynamic Selection And Replacement Of Executable Embodiments With Temporally Optimal Functional Detail And Simplification
US Patent:
2010002, Jan 28, 2010
Filed:
Feb 17, 2009
Appl. No.:
12/372014
Inventors:
John Christopher Willis - Rochester MN, US
Joshua Alan Johnson - Rochester MN, US
Ruth Ann Betcher - Rochester MN, US
Joshua Alan Johnson - Rochester MN, US
Ruth Ann Betcher - Rochester MN, US
Assignee:
FTL Systems, Inc. - Rochester MN
International Classification:
G06G 7/62
US Classification:
703 13
Abstract:
A method for increasing simulation speed is achieved by implementing a sequence of executable embodiments of digital, analog, mixed-signal or full-wave components are substituted during the process. The substituted embodiments represent more optimal instruction sequences, reconfigurable logic configurations or combinations thereof which may only be a valid representation of the model being simulated, subject to specific operating conditions.
Simulation Of Designs Using Programmable Processors And Electronically Re-Configurable Logic Arrays
US Patent:
2003014, Aug 7, 2003
Filed:
Nov 20, 2002
Appl. No.:
10/301423
Inventors:
John Willis - Rochester MN, US
Joshua Johnson - Rochester MN, US
Ruth Betcher - Rochester MN, US
Joshua Johnson - Rochester MN, US
Ruth Betcher - Rochester MN, US
International Classification:
G06F009/44, G06G007/62, G06F015/00
US Classification:
717/135000, 703/013000, 712/015000
Abstract:
A means of increasing the steady-state simulation speed of a design comprising digital, analog, mixed-signal and full-wave components is taught using general purpose processors and electronically re-configurable logic. The innovative compilation and execution method disclosed uses either a single compilation step before the onset of simulation or incremental compilation during simulation to yield multiple, optimized processor instructions, logic configurations and interconnect configurations specific to the operating contexts encountered during execution embedded within a pseudo-static execution schedule. Caching provides for rapid re-use of compilation results specific to an operating context. Key innovative steps embodied in the apparatus include use of to represent time-varying changes in design state rather than the actual value of design state at each time point, encapsulation of component model functionality, dynamically varying numerical range in hardware, and integration of a reduced latency interconnect in close proximity to the acceleration resources.
Solid State Storage End Of Life Prediction With Correction History
US Patent:
7975193, Jul 5, 2011
Filed:
Jun 1, 2009
Appl. No.:
12/475716
Inventors:
Joshua Johnson - Rochester MN, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11C 29/00
US Classification:
714723, 714 2, 714 5, 714 7, 714 25, 714 30, 714 31, 714 42, 714704, 714718, 714721, 714745, 711102, 711103, 36518501, 36518533
Abstract:
Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data.
Architecture For Nand Flash Constraint Enforcement
US Patent:
2010030, Dec 2, 2010
Filed:
Jun 1, 2009
Appl. No.:
12/475710
Inventors:
Joshua Johnson - Rochester MN, US
International Classification:
G06F 12/00, G06F 12/02
US Classification:
711103, 711E12001, 711E12008
Abstract:
Described embodiments provide for constraint checking for constraints imposed on NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device. In the illustrative implementation, the data processing and storage management paradigm allows for the storage of data according using a selected constraint enforcement algorithm. A NAND data storage constraint checking module can be operable to enforce one or more selected device constraints with one or more co-operating components to the NAND data store.
Low Power Physical Layer For Sata And Sas Transceivers
US Patent:
2010025, Sep 30, 2010
Filed:
Mar 27, 2009
Appl. No.:
12/412641
Inventors:
Joshua Johnson - Rochester MN, US
David Smith - Rochester MN, US
Steven Schauer - Loveland CO, US
David Morgan - Fort Collins CO, US
David Smith - Rochester MN, US
Steven Schauer - Loveland CO, US
David Morgan - Fort Collins CO, US
International Classification:
G06F 3/00
US Classification:
710 18
Abstract:
Described embodiments provide for switching from a low-power mode of a device such as, for example, a SAS or SATA receiver, to an active mode. The device enters the low-power mode by shutting down i) logic devices of a physical layer of the device and ii) a decoding circuit of the device. Activity at an input of a receiver of the device is detected while in low-power mode, and the device switches, in response to the detected activity, from the low-power mode to the active mode by powering up i) the logic devices of the physical layer and ii) the decoding circuit when activity is detected, thereby responding to the detected activity as if it is a predetermined command.