JOSEPH TATE EVANS, JR
Pilots at Verbena Pl, Albuquerque, NM

5679969, Oct 21, 1997

Jun 11, 1996

8/661597

Joseph T. Evans - Albuquerque NM
Richard H. Womack - Albuquerque NM

Radiant Technologies, Inc. - Albuquerque NM

H01L 27108, H01L 2976, H01L 2994, H01L 3162

257295

A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO. sub. 2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

5892255, Apr 6, 1999

Oct 12, 1997

8/946749

Joseph T. Evans - Albuquerque NM
Richard H. Womack - Albuquerque NM

Radiant Technologies - Albuquerque NM

H01L 27108, H01L 2976, H01L 2994, H01L 3162

257295

A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO. sub. 2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

5963466, Oct 5, 1999

Apr 13, 1998

9/059606

Joseph T. Evans - Albuquerque NM

Radiant Technologies, Inc. - Albuquerque NM

G11C 1122, H01L 2976

365145

A memory for storing a plurality of words of data. The memory is constructed from one or more storage blocks. Each storage block includes a plurality of storage words, each storage word storing one of the words of data. Each storage word includes a plurality of single bit storage cells. The single bit storage cells include a ferroelectric capacitor and a pass transistor having a gate, source, and drain. The ferroelectric capacitor includes a bottom electrode, a layer of ferroelectric material, and a top electrode, the layer of ferroelectric material being sandwiched between the top and bottom electrodes. One bit of data is stored in the direction of polarization of the ferroelectric material in contact with the bottom electrode. The bottom electrode is connected to the source of the pass transistor. The top electrode of each single bit storage cell is part of a continuous conducting layer covering all of the ferroelectric capacitors in the storage block.

5578846, Nov 26, 1996

Mar 17, 1995

8/406386

Joseph T. Evans - Albuquerque NM
William L. Warren - Albuquerque NM
Bruce A. Tuttle - Albuquerque NM

H01L 2978

257295

An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO. sub. 3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively.

5164808, Nov 17, 1992

Aug 9, 1991

7/738897

Joseph T. Evans - Albuquerque NM
Jeff A. Bullington - Albuquerque NM
Carl E. Montross - Albuquerque NM

Radiant Technologies - Albuquerque NM

H01L 2966

361305

An improved ferroelectric structure and the method for making the same is disclosed. The improved structure reduces the fatigue problems encountered in ferroelectric capacitors while providing avoiding problems in depositing the ferroelectric material which have prevented other solutions to the fatigue problem from being effective. The improved ferroelectric structure also provides improved adhesion to the underlying substrate. The ferroelectric structure has a bottom electrode comprising a layer of PtO. sub. 2 which is generated by depositing a layer of Platinum on a suitable substrate and then exposing the Platinum layer to an Oxygen plasma. The ferroelectric material is then deposited on the PtO. sub. 2 layer.

5212620, May 18, 1993

Mar 3, 1992

7/845064

Joseph T. Evans - Albuquerque NM
Jeff A. Bullington - Albuquerque NM
Carl E. Montross - Albuquerque NM

Radiant Technologies - Albuquerque NM

H01G 410, H01G 700, G11C 1122

361313

An improved method for constructing integrated circuit structures in which a buffer SiO. sub. 2 layer is used to separate various components comprising ferroelectric materials or platinum is disclosed. The invention prevents interactions between the SiO. sub. 2 buffer layer and the ferroelectric materials. The invention also prevents the cracking in the SiO. sub. 2 which is commonly observed when the SiO. sub. 2 layer is deposited directly over a platinum region on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material and which is also an electrical insulator to separate the SiO. sub. 2 layer from the ferroelectric material and/or the platinum regions.

6225654, May 1, 2001

May 1, 1996

8/640572

Joseph T. Evans - Albuquerque NM
William L. Warren - Albuquerque NM
Bruce A. Tuttle - Albuquerque NM

Radiant Technologies, Inc - Albuquerque NM

B05D 512

257295

An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO. sub. 3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively.

4654586, Mar 31, 1987

Jun 10, 1985

6/742826

Joseph T. Evans - Albuquerque NM
Stacy M. Munechika - Albuquerque NM
Michael C. Norris - Albuquerque NM
Alisa M. Hren - Albuquerque NM
Kevin M. Heck - Albuquerque NM
Suzanne M. Zulka - Albuquerque NM

The United States of America as represented by the Secretary of the Air
Force - Washington DC

G01R 2508

324 83D

A digital phase meter to measure the phase difference between an input signal and a reference signal and output this phase information in the form of an eight bit number. The input signal and the reference signal, which are sinusoidal, are conditioned to a more defined leading edge by a high speed differential voltage comparator and a dual/differential line receiver. A series of uniquely configured D flip-flops are used to detect the leading edge of both the signal input and the reference input. An AND gate then acts as a switch that is activated on the leading edge of the signal input. The time interval between the two positive leading edges of the input signal and reference signal specifies the phase difference. The AND gate is in the high state for this duration. The phase difference is converted into an 8-bit binary number via two 4-bit cascaded counters.

5119329, Jun 2, 1992

May 13, 1991

7/699491

Joseph T. Evans - Albuquerque NM
Jeff A. Bullington - Albuquerque NM

Radiant Technologies - Albuquerque NM

G11C 1122

365145

An improved memory device based on a non-volatile variable resistance element is disclosed. The resistive element is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferro-electric layer. The semiconductor forms one plate of a parallel plate capacitor having a dielectric comprising the ferro-electric layer. The state of the memory device is determined by measuring the resistivity of the semiconductor layer between two contacts on the semiconductor layer. The state of polarization of the ferro-electric layer is altered by applying a voltage between one of these contacts and the other plate of the capacitor.

5614438, Mar 25, 1997

Mar 15, 1995

8/405216

Joseph T. Evans - Albuquerque NM
Leonard Boyer - Albuquerque NM

Radiant Technologies, Inc. - Albuquerque NM

H01L 2144

437192

A method for making an improved LSCO stack in the generation of platinum features on the surface of a substrate. The method provides an inexpensive means for depositing and etching LSCO material in the construction of small platinum features. The method comprises sputtering of the LSCO material and utilizing a photoresist mask to pattern the LSCO in accordance with the platinum features. The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.