JOSEPH S MINACAPELLI
Pilots at Ln Rochelle Ter, Sunnyvale, CA
License number
California A2706426
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
1168 La Rochelle Ter E APT E, Sunnyvale, CA 94089
Professional information
System With A High Power Chip And A Low Power Chip Having Low Interconnect Parasitics
US Patent:
2013005, Mar 7, 2013
Filed:
Sep 7, 2011
Appl. No.:
13/227328
Inventors:
Abraham F. YEE - Cupertino CA, US
Joe Greco - San Jose CA, US
Jun Zhai - San Jose CA, US
Joseph Minacapelli - Sunnyvale CA, US
John Y. Chen - Cupertino CA, US
Joe Greco - San Jose CA, US
Jun Zhai - San Jose CA, US
Joseph Minacapelli - Sunnyvale CA, US
John Y. Chen - Cupertino CA, US
International Classification:
H05K 7/00
US Classification:
361820
Abstract:
An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.
Apparatus, System, And Method For Designing Via Pads Having Extended Contours
US Patent:
7353480, Apr 1, 2008
Filed:
Dec 7, 2004
Appl. No.:
11/007560
Inventors:
Joseph S. Minacapelli - Sunnyvale CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 10, 716 11, 716 12
Abstract:
An apparatus to design a via pad of a via is described. In one embodiment, the apparatus includes a vertex determination module configured to determine a vertex of the via pad based on a position of a trace that is connected to the via. The apparatus also includes a contour definition module configured to define an extended contour of the via pad based on the vertex. The extended contour is defined such that an electrical length design characteristic of the trace is substantially unchanged by the extended contour.
Multi-Configuration Gpu Interface Device
US Patent:
2004001, Jan 22, 2004
Filed:
Jul 16, 2002
Appl. No.:
10/197071
Inventors:
Thomas Dewey - Menlo Park CA, US
James Dobbins - Santa Clara CA, US
Joseph Minacapelli - Sunnyvale CA, US
Simon Thomas - Campbell CA, US
James Dobbins - Santa Clara CA, US
Joseph Minacapelli - Sunnyvale CA, US
Simon Thomas - Campbell CA, US
International Classification:
H01L027/10
US Classification:
257/686000
Abstract:
A multi-configuration interface device for coupling different types of GPUs (graphics processor units) to a PCB (printed circuit board). The interface device comprises a GPU interface for a connection to the GPU and a PCB interface for a connection to the PCB. The GPU interface is implemented using a customizable attachment footprint for effectuating a connection to differing GPU types while maintaining the PCB interface for the connection to the PCB. The ball array for different GPUs can be configured to respectively support them. The interface device maintains a consistent PCB interface. Thus, as GPU characteristics change and evolve, or as different GPU versions are implemented, a consistent connection can be maintained for the PCB.