DR. JOSEPH PATRICK BROOKS, MD
Radiology at Curtis Rd, Boise, ID

License number
Idaho 2009-00298
Category
Radiology
Type
Therapeutic Radiology
License number
Idaho M-11219
Category
Radiology
Type
Therapeutic Radiology
Address
Address 2
1055 N Curtis Rd, Boise, ID 83706
3340 E GOLDSTONE WAY, Meridian, ID 83642
Phone
(208) 367-3131
(208) 367-4860 (Fax)

Professional information

Joseph Patrick Brooks Photo 1

Joseph Patrick Brooks, Boise ID

Specialties:
Radiologist
Address:
1055 N Curtis Rd, Boise, ID 83706
Education:
Thomas Jefferson University, Jefferson Medical College - Doctor of Medicine
Board certifications:
American Board of Radiology Certification in Radiation Oncology (Radiology)


Joseph Brooks Photo 2

Joseph Brooks, Boise ID

Work:
St Alphonsus Regional Medical Center
1055 N Curtis Rd, Boise, ID 83706 Saint Alphonsus Cancer Care Center
3123 Medical Dr, Caldwell, ID 83605


Joseph Brooks Photo 3

Access Transistor For Memory Device

US Patent:
2010017, Jul 15, 2010
Filed:
Mar 24, 2010
Appl. No.:
12/730611
Inventors:
Jon Daley - Boise ID, US
Kristy A. Campbell - Boise ID, US
Joseph F. Brooks - Boise ID, US
International Classification:
H01L 21/8239
US Classification:
438238, 257E21645
Abstract:
An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.


Joseph Brooks Photo 4

Access Transistor For Memory Device

US Patent:
7579615, Aug 25, 2009
Filed:
Aug 9, 2005
Appl. No.:
11/199251
Inventors:
Jon Daley - Boise ID, US
Kristy A. Campbell - Boise ID, US
Joseph F. Brooks - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 45/00
US Classification:
257 5, 257E45002, 365163
Abstract:
An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.