JOSEPH P LORENZO
Broker in Stow, MA

License number
Massachusetts 133934
Issued Date
Jan 25, 1988
Expiration Date
Feb 10, 2016
Type
Broker
Address
Address
Stow, MA 01775

Personal information

See more information about JOSEPH P LORENZO at radaris.com
Name
Address
Phone
Joseph Lorenzo
540 Columbia Rd, Dorchester, MA 02125
Joseph Lorenzo
13 Bay Rd, Harwich, MA 02645
(508) 430-4038
Joseph Lorenzo
257 Westville St, Dorchester, MA 02122
Joseph Lorenzo, age 40
100 Temple Dr, Methuen, MA 01844
(978) 687-7846
(978) 974-9068
Joseph A Lorenzo, age 85
13 Bay Rd, East Harwich, MA 02645
(508) 430-4038
(508) 432-5014

Professional information

See more information about JOSEPH P LORENZO at trustoria.com
Joseph Lorenzo Photo 1
Metal-Insulator-Semiconductor Control Of Guided Optical Waves In Semiconductor Waveguides

Metal-Insulator-Semiconductor Control Of Guided Optical Waves In Semiconductor Waveguides

US Patent:
4877299, Oct 31, 1989
Filed:
Mar 15, 1989
Appl. No.:
7/323736
Inventors:
Joseph P. Lorenzo - Stow MA
Richard A. Soref - Newton Centre MA
Assignee:
United States of America as represented by the Secretary of the Air Force - Washington DC
International Classification:
G02B 610
US Classification:
350 9614
Abstract:
This invention describes an infrared lightwave modulation and switching aratus for very rapidly changing the refractive index of a light-transmitting, doped, semiconductor waveguide. Electrical control is exerted by a MIS diode or MISFET. The apparatus includes a transparent crystalline silicon waveguide, an electrically insulating dielectric layer overlaying a portion of that waveguide, and an elongated, conductive gate electrode in contact with the insulator. A gate voltage applied between the semiconductor and gate serves to deplete free charge carriers from the region of the waveguide under the gate. Elongated source and drain electrodes may be added to enhance electro-optic control.


Joseph Lorenzo Photo 2
Cadmium Sulfide Interface Layers For Improving Iii-V Semiconductor Device Performance And Characteristics

Cadmium Sulfide Interface Layers For Improving Iii-V Semiconductor Device Performance And Characteristics

US Patent:
5689125, Nov 18, 1997
Filed:
Jun 12, 1995
Appl. No.:
8/489601
Inventors:
Kenneth Vaccaro - Acton MA
Andrew Davis - Boston MA
Helen M. Dauplaise - Brockton MA
Joseph P. Lorenzo - Stow MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
H01L 29778, H01L 310328
US Classification:
257200
Abstract:
In a Schottky metal junction semiconductor device, a CdS interface layer, having a thickness of under 100 angstroms, is positioned under the Schottky barrier gate of a III-V HEMT, for reducing gate leakage, and for enabling full depletion of the conducting channel. A similar layer is positioned under the insulator of an MIS device having an InP substrate. The CdS layers are deposited from a chemical bath which merely entails a simple, safe and readily controllable additional step in the otherwise conventional manufacturing process of these devices.


Joseph Lorenzo Photo 3
Fet Optical Receiver Using Backside Illumination, Indium Materials Species

Fet Optical Receiver Using Backside Illumination, Indium Materials Species

US Patent:
5532173, Jul 2, 1996
Filed:
Jul 14, 1994
Appl. No.:
8/274930
Inventors:
Eric A. Martin - Medford MA
Kenneth Vaccaro - Acton MA
William Waters - Glassborn NJ
Joseph P. Lorenzo - Stow MA
Stephen Spaziani - Nashua NH
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
H01L 3118
US Classification:
437 2
Abstract:
A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.


Joseph Lorenzo Photo 4
Electrically Controlled Integrated Optical Switch

Electrically Controlled Integrated Optical Switch

US Patent:
4746183, May 24, 1988
Filed:
May 18, 1987
Appl. No.:
7/050358
Inventors:
Richard A. Soref - Newton Centre MA
Joseph P. Lorenzo - Stow MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
G02B 610
US Classification:
350 9614
Abstract:
An electrically controlled integrated optical switch having a body made up entirely of crystalline silicon. More specifically, the body has a pair of channel waveguides intersecting in an X-like configuration forming therein an intersection crossover region. A first electrode is positioned on the intersection crossover region and a second electrode is positioned on the bottom of the body opposite the intersection crossover region. A controllable current/voltage source is electrically connected to the electrodes in order to alter the index of refraction of the intersection crossover region by carrier injection in order to selectively switch optical signals between diverging waveguides.


Joseph Lorenzo Photo 5
Lattice Mismatched Hetrostructure Optical Waveguide

Lattice Mismatched Hetrostructure Optical Waveguide

US Patent:
5163118, Nov 10, 1992
Filed:
Aug 26, 1988
Appl. No.:
7/237244
Inventors:
Joseph P. Lorenzo - Stow MA
Richard A. Soref - Newton MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
G02P 610
US Classification:
385132
Abstract:
The invention comprises processes and heterostructure products defining silicon on insulator waveguides (80, 88, 90, 106, 112, 120, 122) that are suitable for use with light in the 1. 3, 1. 6. mu. m or greater wavelengths. Silicon is deposited on an insulator layer 12 on a crystalline substrate 10 and grown or regrown in crystalline form. The silicon is then etched or formed into a waveguide structures.


Joseph Lorenzo Photo 6
Method For Fabricating Low Loss Crystalline Silicon Waveguides By Dielectric Implantation

Method For Fabricating Low Loss Crystalline Silicon Waveguides By Dielectric Implantation

US Patent:
4789642, Dec 6, 1988
Filed:
Mar 26, 1987
Appl. No.:
7/032810
Inventors:
Joseph P. Lorenzo - Stow MA
Richard A. Soref - Newton Centre MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
H01L 21425, G02B 610
US Classification:
437 24
Abstract:
A method of fabricating low loss silicon optical waveguides by high energy ion implantation which converts a buried region into dielectric material. The top silicon surface can them be etched or formed into waveguides that are isolated by the buried dielectric. Annealing of the top silicon layer can be used to improve optical quality and additional silicon can be added to the top surface waveguides by epitaxial growth.


Joseph Lorenzo Photo 7
Wafer Joined Optoelectronic Integrated Circuits And Method

Wafer Joined Optoelectronic Integrated Circuits And Method

US Patent:
5472914, Dec 5, 1995
Filed:
Jul 14, 1994
Appl. No.:
8/274882
Inventors:
Eric A. Martin - Medford MA
Kenneth Vaccaro - Acton MA
Joseph P. Lorenzo - Stow MA
Andrew Davis - Boston MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
H01L 2160
US Classification:
437209
Abstract:
A full wafer to full wafer integrated circuit fabrication process wherein substrate removal and replacement of one wafer is used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo field effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.


Joseph Lorenzo Photo 8
Optically Controlled Integrated Optical Switch

Optically Controlled Integrated Optical Switch

US Patent:
4693547, Sep 15, 1987
Filed:
Feb 24, 1986
Appl. No.:
6/831910
Inventors:
Richard A. Soref - Newton Centre MA
Joseph P. Lorenzo - Stow MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
G02B 610
US Classification:
350 9613
Abstract:
An optically controlled integrated optical switch having a body made up of entirely crystalline silicon. More specifically, the body has a pair of channel waveguides intersecting at an X-like configuration forming therein an intersection crossover region. An electrically controlled optical source is positioned over the crossover region to shine intense, short wavelight on the crossover region in order to generate numerous electron-hole pairs in the waveguide material. These charge carriers alter the refractive index of the intersection region. A controllable current source is used to adjust the optical output power of the optical source. This, in turn, changes the amount of optical cross coupling of light between the intersecting waveguides.


Joseph Lorenzo Photo 9
Backside Illuminated Msm Device Method

Backside Illuminated Msm Device Method

US Patent:
5494833, Feb 27, 1996
Filed:
Jul 14, 1994
Appl. No.:
8/274889
Inventors:
Eric A. Martin - Medford MA
Kenneth Vaccaro - Acton MA
Joseph P. Lorenzo - Stow MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Wright-Patterson Air Force Base OH
International Classification:
H01L 3118
US Classification:
437 2
Abstract:
An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.


Joseph Lorenzo Photo 10
Method Of Making A Lattice Mismatched Heterostructure Optical Waveguide

Method Of Making A Lattice Mismatched Heterostructure Optical Waveguide

US Patent:
5354709, Oct 11, 1994
Filed:
Apr 11, 1991
Appl. No.:
7/683924
Inventors:
Joseph P. Lorenzo - Stow MA
Richard A. Soref - Newton MA
Assignee:
The United States of America as represented by the Secretary of the Air
Force - Washington DC
International Classification:
H01L 2120
US Classification:
437129
Abstract:
The invention comprises processes and heterostructure products defining silicon on insulator waveguides (80, 88, 90, 106, 112, 120, 122) that are suitable for use with light in the 1. 3, 1. 6. mu. m or greater wavelengths. Silicon is deposited on an insulator layer 12 on a crystalline substrate 10 and grown or regrown in crystalline form. The silicon is then etched or formed into a waveguide structures.