JOSEPH L CUMBO
Engineers in Pittston, PA

6680232, Jan 20, 2004

Sep 19, 2001

09/956568

Thomas E. Grebs - Mountaintop PA
Joseph L. Cumbo - West Wyoming PA

Fairchild Semiconductor Corporation - South Portland ME

H01L 21336

438270, 438589, 438702, 438714, 438719, 438958, 438978

A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.

6673681, Jan 6, 2004

Jun 19, 2002

10/174641

Christopher B. Kocon - Plains PA
Thomas E. Grebs - Mountaintop PA
Joseph L. Cumbo - West Wyoming PA
Rodney S. Ridley - Mountaintop PA

Fairchild Semiconductor Corporation - South Portland ME

H01L 2976

438270, 438259, 257328, 257329, 257330

A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.

6433385, Aug 13, 2002

Oct 12, 2000

09/689939

Christopher B. Kocon - Plains PA
Thomas E. Grebs - Mountaintop PA
Joseph L. Cumbo - West Wyoming PA
Rodney S. Ridley - Mountaintop PA

Fairchild Semiconductor Corporation - South Portland MA

H01L 2976

257328, 257329, 257330, 438259, 438270

A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench.

5872028, Feb 16, 1999

Sep 5, 1996

8/708712

Joseph Andrew Yedinak - Mountaintop PA
Anup Bhalla - Wilkes-Barre PA
Jeffrey Allen Webster - Wilkes-Barre PA
Joseph Leonard Cumbo - Exeter PA

Harris Corporation - Melbourne FL

H01L 21332

438133

A method of manufacturing a semiconductor device and device in which a sacrificial N shelf layer is grown on a P+ semiconductor substrate to contain the out-diffusion of dopant from the substrate. An N+ buffer layer is grown on the N shelf layer and an N- epitaxial layer is grown on the N+ buffer layer. The presence of the N shelf layer, which is consumed by the substrate dopant during further device fabrication, allows the integrated dopant level of the N+ buffer layer to be accurately controlled in the finished device.

6211550, Apr 3, 2001

Jun 24, 1999

9/339356

Thomas Eugene Grebs - Mountaintop PA
Rodney Sylvester Ridley - Mountaintop PA
Jeffrey P. Spindler - Rochester NY
Joseph Leonard Cumbo - West Wyoming PA
Jeffrey Edward Lauffer - Mountaintop PA

Intersil Corporation - Palm Bay FL

H01L 2976, H01L 2348, H01L 2352, H01L 2940

257342

A semiconductor device includes a source region and a gate disposed at the upper surface of a silicon substrate, which includes a drain region for the device. On the lower surface of the substrate is disposed a backmetal drain terminal comprising a stack that includes a first layer of tantalum and an outermost second layer of copper.

2002016, Oct 31, 2002

Mar 1, 2001

09/797323

Thomas Grebs - Mountaintop PA, US
Joseph Cumbo - West Wyoming PA, US

H01L021/302, H01L021/461

438/704000, 438/745000

Trenches are made in an integrated circuit by a process that incrementally increases the amount of oxygen during a trench etch. The trench may be an isolation trench or a gate trench for a QVDMOS device.