JOSEPH A TAYLOR, III
Pharmacy at Greenpointe Dr, Orlando, FL
License number
Florida 46694
Issued Date
Jan 23, 2013
Effective Date
Jan 26, 2017
Expiration Date
Dec 31, 2014
Category
Health Care
Type
Registered Pharmacy Technician
Address
Address
13220 Greenpointe Dr, Orlando, FL 32824
Phone
(407) 452-9401
Organization information
See more information about JOSEPH A TAYLOR at bizstanding.comJoseph Taylor
Orlando, FL
Status:
Inactive
Industry:
Automotive Services
Doing business as:
Tb Towing & Recovery
Addresses:
7160 Ironwood Dr, Orlando, FL 32818
PO Box 616196, Orlando, FL 32861
PO Box 616196, Orlando, FL 32861
Principal:
Carol Montford Principal, inactive
Professional information
Media Manager At Deltak
Position:
Media Manager at Deltak
Location:
Orlando, Florida Area
Industry:
Marketing and Advertising
Work:
Deltak
- Orlando, Florida Area since Jan 2013
-
Media Manager
Deltak
Jul 2011 - May 2013
-
PPC Manager
Deltak
- Maitland, FL May 2010 - Jul 2011
-
Associate Marketing Manager
University of Central Florida
Feb 2010 - May 2010
-
Marketing Intern
Ypartnership
Jan 2010 - May 2010
-
Consumer Insights Intern
Engauge
Aug 2008 - Aug 2009
-
Advertising and Public Relations Intern
Education:
Benedictine University 2012 - 2014
Master of Business Administration (M.B.A.), Internet Marketing University of Central Florida 2007 - 2010
Bachelor of Arts, Advertising and Public Relations University of Central Florida 2007 - 2010
Bachelor of Science, Psychology
Master of Business Administration (M.B.A.), Internet Marketing University of Central Florida 2007 - 2010
Bachelor of Arts, Advertising and Public Relations University of Central Florida 2007 - 2010
Bachelor of Science, Psychology
Certifications:
Google Adwords Certification, Google
Pay Per Click Advertising, Market Motive
Pay Per Click Advertising, Market Motive
Method Of Forming A Reverse Gate Structure With A Spin On Glass Process
US Patent:
6506673, Jan 14, 2003
Filed:
Jun 11, 2001
Appl. No.:
09/878690
Inventors:
Yi Ma - Orlando FL
Huili Shao - Allentown PA
Joseph A. Taylor - Orlando FL
Allen Yen - Allentown PA
Huili Shao - Allentown PA
Joseph A. Taylor - Orlando FL
Allen Yen - Allentown PA
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H01L 214763
US Classification:
438622, 438 99, 438183, 438623, 438692
Abstract:
The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.
Method And Apparatus For Controlling The Movement Of A Liquid On A Nanostructured Or Microstructured Surface
US Patent:
2004019, Sep 30, 2004
Filed:
Mar 31, 2003
Appl. No.:
10/403159
Inventors:
Avinoam Kornblit - Highland Park NJ, US
Timofei Kroupenkine - Warren NJ, US
Mary Mandich - Martinsville NJ, US
Tobias Schneider - Marburg, DE
Joseph Taylor - Orlando FL, US
Shu Yang - New Providence NJ, US
Timofei Kroupenkine - Warren NJ, US
Mary Mandich - Martinsville NJ, US
Tobias Schneider - Marburg, DE
Joseph Taylor - Orlando FL, US
Shu Yang - New Providence NJ, US
International Classification:
B01L003/02
US Classification:
422/100000
Abstract:
A method and apparatus is disclosed wherein the movement of a droplet disposed on a nanostructured or microstructured surface is determined by at least one characteristic of the nanostructure feature pattern or at least one characteristic of the droplet. In one embodiment, the movement of the droplet is laterally determined by at least one characteristic of the nanostructure feature pattern such that the droplet moves in a desired direction along a nanostructured feature pattern. In another embodiment, the movement of the droplet is determined by either at least one characteristic of the nanostructure feature pattern or at least one characteristic of the droplet in a way such that the droplet penetrates the feature pattern at a desired area and becomes substantially immobile.
Mask Layer And Dual Damascene Interconnect Structure In A Semiconductor Device
US Patent:
2003011, Jun 26, 2003
Filed:
Dec 21, 2001
Appl. No.:
10/026257
Inventors:
Robert Huang - Ocoee FL, US
Scott Jessen - Orlando FL, US
Subramanian Karthikeyan - Orlando FL, US
Joshua Li - Orlando FL, US
Isaiah Oladeji - Gotha FL, US
Kurt Steiner - Orlando FL, US
Joseph Taylor - Orlando FL, US
Scott Jessen - Orlando FL, US
Subramanian Karthikeyan - Orlando FL, US
Joshua Li - Orlando FL, US
Isaiah Oladeji - Gotha FL, US
Kurt Steiner - Orlando FL, US
Joseph Taylor - Orlando FL, US
International Classification:
H01L021/4763
US Classification:
438/633000
Abstract:
A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
Devices And Method Of Their Manufacture
US Patent:
2004024, Dec 9, 2004
Filed:
Jun 6, 2003
Appl. No.:
10/456659
Inventors:
Chien-Shing Pai - Bridgewater NJ, US
Stanley Pau - Hoboken NJ, US
Joseph Taylor - Orlando FL, US
Stanley Pau - Hoboken NJ, US
Joseph Taylor - Orlando FL, US
International Classification:
B44C001/22
US Classification:
216/058000
Abstract:
In fabricating an apparatus such as a silicon device or an optical device initially a wafer having a plurality of dies is formed. These dies are then separated into individual dies and the individual dies are formed into encapsulated devices having input and/or output leads. The dies are separated by a means that is not based on crystallographic plane cleavage. Additionally the boundary along which the separation is performed is not a linear path. By employing non-linear paths that are not constrained by crystallographic planes, device yield per wafer is substantially improved particularly for dies having non-linear boundaries. In one embodiment the dies are separated using an alternating dry etching and polymer deposition technique.
Mask Layer And Interconnect Structure For Dual Damascene Semiconductor Manufacturing
US Patent:
2004017, Sep 2, 2004
Filed:
Nov 2, 2003
Appl. No.:
10/699975
Inventors:
Isaiah Oladeji - Gotha FL, US
Scott Jessen - Orlando FL, US
Joseph Taylor - Orlando FL, US
Scott Jessen - Orlando FL, US
Joseph Taylor - Orlando FL, US
International Classification:
H01L021/302
US Classification:
438/689000
Abstract:
A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over the passivation film and a metallic film is deposited over the barrier film. The metallic film increases the overall etch selectivity of the mask layer to assure a faithful transfer of via and trench features to the low-k dielectric material during the etching steps of the dual damascene process.
Mask Layer And Dual Damascene Interconnect Structure In A Semiconductor Device
US Patent:
7067419, Jun 27, 2006
Filed:
Nov 25, 2003
Appl. No.:
10/721126
Inventors:
Robert Y S Huang - Ocoee FL, US
Scott Jessen - Orlando FL, US
Subramanian Karthikeyan - Orlando FL, US
Joshua Jia Li - Vancouver WA, US
Isaiah O. Oladeji - Orlando FL, US
Kurt George Steiner - Orlando FL, US
Joseph Ashley Taylor - Orlando FL, US
Scott Jessen - Orlando FL, US
Subramanian Karthikeyan - Orlando FL, US
Joshua Jia Li - Vancouver WA, US
Isaiah O. Oladeji - Orlando FL, US
Kurt George Steiner - Orlando FL, US
Joseph Ashley Taylor - Orlando FL, US
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
H01L 21/467
US Classification:
438638, 438736, 438738
Abstract:
A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.
Mask Layer And Interconnect Structure For Dual Damascene Semiconductor Manufacturing
US Patent:
2003006, Apr 3, 2003
Filed:
Sep 28, 2001
Appl. No.:
09/966157
Inventors:
Isaiah Oladeji - Gotha FL, US
Scott Jessen - Orlando FL, US
Joseph Taylor - Orlando FL, US
Scott Jessen - Orlando FL, US
Joseph Taylor - Orlando FL, US
International Classification:
H01L021/4763
US Classification:
438/638000, 438/618000
Abstract:
A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over the passivation film and a metallic film is deposited over the barrier film. The metallic film increases the overall etch selectivity of the mask layer to assure a faithful transfer of via and trench features to the low-k dielectric material during the etching steps of the dual damascene process.