JOSEPH A CICCIO
Broker in Winchester, MA

License number
Massachusetts 60139
Issued Date
Jun 1, 1968
Expiration Date
Jun 2, 1992
Type
Broker
Address
Address
Winchester, MA 01890

Personal information

See more information about JOSEPH A CICCIO at radaris.com
Name
Address
Phone
Joseph Ciccio
119 Ridge St, Winchester, MA 01890
Joseph Ciccio
72 Pheasant Ln, East Falmouth, MA 02536
Joseph Ciccio
119 Ridge St, Winchester, MA 01890
Joseph Ciccio
1 Pheasant Ln, Barnstable, MA 02630

Professional information

Joseph Ciccio Photo 1

Integrated Circuit Device Package Interconnect Means

US Patent:
4225900, Sep 30, 1980
Filed:
Oct 25, 1978
Appl. No.:
5/954513
Inventors:
Joseph A. Ciccio - Winchester MA
Rudolf E. Thun - Carlisle MA
Harry J. Fardy - Chelmsford MA
Assignee:
Raytheon Company - Lexington MA
International Classification:
H05K 108
US Classification:
361395
Abstract:
An integrated circuit device package is disclosed wherein a pair of dielectric support structures are provided, each one having a pattern of electrical conductors for interconnecting integrated circuit devices disposed thereon. The electrical conductors have end portions terminating into a plurality of contact pads disposed on a first surface of the support structures. A first one of the pair of support structures has corresponding contact pads on a second, opposite surface of the support structure, each one of the contact pads on the first surface being electrically connected to a corresponding one of the contact pads on the second surface. A dielectric spacer having a plurality of electrical contact pins is disposed between the pair of support structures. One end of each pin is electrically connected to a corresponding one of the contact pads disposed on the second surface of the first one of such structures, and the other end of such contact pin is electrically connected to a corresponding one of the contact pins disposed on the first surface of the second one of the structures. The contact pins are relatively short and thereby provide a relatively short electrical interconnect for the integrated circuit devices, thereby reducing parasitic capacitances normally associated with electrical interconnects.