JOSE ANTONIO LYON
Pilots at Antoinette Pl, Austin, TX

5185607, Feb 9, 1993

Jan 31, 1992

7/829113

Jose A. Lyon - Austin TX
Jules D. Campbell - Austin TX

Motorola, Inc. - Schaumburg IL

H03M 110

341120

A method and apparatus for testing an analog to digital converter (14) having a resistor digital to analog converter (32). In one form, the analog to digital converter uses a small amount of resistor test logic (44) to test for defects in the resistor array (42), the switch array (38), and the optional decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry, which includes some analog circuitry, is tested by using a pull-up function and a pull-down function that can be overdriven by properly functioning circuitry. As a result of using resistor test logic (44), a very quick pass/fail functional test using digital logic levels as inputs can be performed on the analog to digital converter (14). The quick functional test does not require analog inputs or time-consuming analog to digital conversions.

5276857, Jan 4, 1994

Apr 26, 1991

7/692350

Eytan Hartung - Austin TX
Jose A. Lyon - Austin TX
Michael E. Gladden - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 100

395550

Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i. e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.

5175547, Dec 29, 1992

Jan 31, 1992

7/829136

Jose A. Lyon - Austin TX
Jules D. Campbell - Austin TX

Motorola, Inc. - Schaumburg IL

H03M 110

341120

A method and apparatus for testing an analog to digital converter (14) having a capacitor digital to analog converter (30). In one form, the analog to digital converter uses a small amount of capacitor test logic (44) to test for opens and shorts in the capacitor array (42), the switch logic (38), and the decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by using AND and OR logical functions. As a result of using capacitor test logic (44), a very quick pass/fail functional test can be performed on the analog to digital converter (14) without requiring the analog to digital converter (14) to perform time-consuming analog to digital conversions.

5485466, Jan 16, 1996

Oct 4, 1993

8/131227

Jose A. Lyon - Austin TX
Tony Cheng - Austin TX
Anthony M. Reipold - Austin TX
Eric Hoang - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1700

371 223

A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.

2006000, Jan 12, 2006

Jul 12, 2004

10/889159

Paul Gelencser - Austin TX, US
Jose Lyon - Austin TX, US

G11C 29/00

365200000

An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array () is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (). A selected one of these vectors stored in the actual solution storage circuitry () is then used to determine rows and columns in memory array () to be replaced with redundant rows () and redundant columns ().

7444568, Oct 28, 2008

Feb 16, 2006

11/355681

Gary R. Morrison - Austin TX, US
Jose A. Lyon - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Anthony M. Reipold - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G01R 31/28

714726, 714738

A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

4972144, Nov 20, 1990

Nov 28, 1989

7/442266

Jose A. Lyon - Austin TX
Paul D. Shannon - Austin TX

Motorola, Inc. - Schaumburg IL

G01R 3128, G06F 1100

524158T

Transistors in a transistor array constructed in a testable multiple channel decoder are tested by setting the array in a test mode. A stuck low test, which detects an open circuit between a source and drain of a transistor, is executed by providing all address lines a first predetermined logic value. A stuck high test, which detects a short between a source and drain of a transistor, is executed by providing a first address line tested a second predetermined logic value and a second logic address line tested the first logic value.