Jonathan Williams Haines
Engineers at Manhattan Dr 211, Boulder, CO
License number
Colorado 53868
Issued Date
Jan 8, 1993
Renew Date
Jan 8, 1993
Type
Engineer Intern
Address
Address
695 Manhattan Dr, Boulder, CO 80303
Professional information
Block Boundary Resolution For Mismatched Logical And Physical Block Sizes
US Patent:
2011009, Apr 28, 2011
Filed:
Oct 23, 2009
Appl. No.:
12/604889
Inventors:
Timothy R. Feldman - Louisville CO, US
Wayne H. Vinson - Longmont CO, US
Jonathan W. Haines - Boulder CO, US
Wayne H. Vinson - Longmont CO, US
Jonathan W. Haines - Boulder CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 9/34
US Classification:
711209, 711E12078
Abstract:
The present disclosure describes various techniques resolving block boundary issues and reconstructing logical blocks in a block access storage device when there are resulting mismatches between logical and physical block sizes or alignments, such that logical blocks span multiple physical block boundaries in irregular ways. In one example, a method comprises the following features: receiving logical block addresses that are associated with a sequence of logical blocks; and locating a first portion of a logical block within a first physical block that is stored in a block access storage device based upon a logical block address of the logical block, wherein the logical block is part of the sequence of logical blocks, and wherein at least two logical blocks within the sequence of logical blocks have different sizes.
Low-Wear Writing In A Solid State Memory Device
US Patent:
8009471, Aug 30, 2011
Filed:
Dec 15, 2009
Appl. No.:
12/638830
Inventors:
Jonathan W. Haines - Boulder CO, US
Tong Shirh Stone - Eden Prairie MN, US
Brett Alan Cook - Longmont CO, US
Tong Shirh Stone - Eden Prairie MN, US
Brett Alan Cook - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G11C 16/04
US Classification:
36518503, 36518517, 36518514, 36518505, 36518906
Abstract:
A method includes programming a non-volatile memory. The memory includes a plurality of cells, wherein each cell is configured to store a plurality of values, wherein each of value is represented by N digits where N is an integer greater than 1, wherein each of the plurality of cells is further configured to store electric charge representing a plurality of voltage levels, and wherein each of the plurality of voltage levels represents one of the plurality of values. Programming comprises providing the plurality of voltage levels into a first group of voltage levels and a second group of voltage levels in one of the plurality of cells, wherein a highest voltage level of the first group is less than or substantially equal to a lowest voltage level of the second group, and storing, in the first group of voltage levels, electric charge representing a value comprising, at most, N-1 digits.
Systems, Methods And Devices For Control Of The Operation Of Data Storage Devices Using Solid-State Memory And Monitoring Energy Used Therein
US Patent:
8468370, Jun 18, 2013
Filed:
Sep 16, 2009
Appl. No.:
12/560868
Inventors:
Michael Howard Miller - Eden Prairie MN, US
Martin Ragnar Furuhjelm - Auburn CA, US
Jonathan Williams Haines - Boulder CO, US
Martin Ragnar Furuhjelm - Auburn CA, US
Jonathan Williams Haines - Boulder CO, US
Assignee:
Seagate Technology LLC - Cupertino CA
International Classification:
G06F 1/00, H02J 7/00, G01R 31/36
US Classification:
713300, 320127, 702 63
Abstract:
A variety of data storage devices, methods and systems are implemented for control of memory associated with backup functionality. One such data storage device includes a power circuit that provides main power. The data storage device has a first solid-state memory circuit that maintains data in the absence of electrical power. A second memory circuit is subject to data loss in the absence of electrical power. A storage circuit stores energy and provides the stored energy to the second memory circuit in response to a loss of main power. A test circuit discharges a portion of the stored energy to provide output data indicative of power-providing capabilities of the storage circuit. A memory controller controls data transfers to the data storage device by temporarily storing data destined for the first solid-state memory circuit and setting the amount of memory available for temporary storage in response to the output data.
Data Management In A Data Storage System
US Patent:
8195909, Jun 5, 2012
Filed:
Oct 5, 2009
Appl. No.:
12/573635
Inventors:
Jonathan Williams Haines - Boulder CO, US
Brett Alan Cook - Westminster CO, US
Timothy Richard Feldman - Louisville CO, US
Paul Michael Wiggins - Longmont CO, US
Brett Alan Cook - Westminster CO, US
Timothy Richard Feldman - Louisville CO, US
Paul Michael Wiggins - Longmont CO, US
Assignee:
Seagate Technology LLC - Cupertino CA
International Classification:
G06F 12/00, G06F 9/46
US Classification:
711170, 711154, 711E12001, 718102
Abstract:
The present disclosure provides a method in a data storage system. The method includes defining a plurality of jobs for a command received from a host. Each of the plurality of jobs is associated with one or more of a plurality of data storage resources of the data storage system. The plurality of jobs have a defined order that is a function of addresses of data in the plurality of data storage resources. The method also includes issuing the plurality of jobs to the associated data storage resources and receiving information from the data storage resources for the plurality of jobs. The information is received by a controller of the data storage system for the jobs in an order that is different than the defined order. The method includes transmitting the received information to the host for the plurality of jobs in the defined order.
Multi-Resolution Cache Monitoring
US Patent:
8631204, Jan 14, 2014
Filed:
Jul 14, 2010
Appl. No.:
12/836296
Inventors:
Jonathan Williams Haines - Boulder CO, US
Wayne Howard Vinson - Boulder CO, US
Edwin Scott Olds - Fort Collins CO, US
Timothy Richard Feldman - Louisville CO, US
Steven S. Williams - Longmont CO, US
Wayne Howard Vinson - Boulder CO, US
Edwin Scott Olds - Fort Collins CO, US
Timothy Richard Feldman - Louisville CO, US
Steven S. Williams - Longmont CO, US
Assignee:
Seagate Technology LLC - Cupertino CA
International Classification:
G06F 12/00
US Classification:
711118, 711E12017
Abstract:
Multi-resolution cache monitoring devices and methods are provided. Multi-resolution cache devices illustratively have a cache memory, an interface, an information unit, and a processing unit. The interface receives a request for data that may be included in the cache memory. The information unit has state information for the cache memory. The state information is organized in a hierarchical structure. The process unit searches the hierarchical structure for the requested data.
Distributed Media Cache For Data Storage Systems
US Patent:
2011016, Jun 30, 2011
Filed:
Dec 31, 2009
Appl. No.:
12/650921
Inventors:
Jonathan Williams Haines - Boulder CO, US
Brett Alan Cook - Longmont CO, US
Brett Alan Cook - Longmont CO, US
Assignee:
SEAGATE TECHNOLOGY LLC - Scotts Valley CA
International Classification:
G06F 12/00, G06F 12/08, G06F 12/02
US Classification:
711103, 711129, 711E12001, 711E12008, 711E12023
Abstract:
This disclosure is related to distributed media cache for data storage systems, such as disc drives, flash devices, or hybrid devices. In one example, a data storage device comprises a data storage medium and a controller adapted to selectively divide a media cache into a plurality of physically separate media cache portions on the data storage medium based on a physical attribute of the data storage medium and to store data received from a host system into the media cache portions.
Dynamic Storage Parameter Tracking
US Patent:
2013023, Sep 12, 2013
Filed:
Mar 12, 2012
Appl. No.:
13/418189
Inventors:
Timothy Richard Feldman - Louisville CO, US
Jonathan Williams Haines - Boulder CO, US
James Joseph Touchton - Boulder CO, US
Jonathan Williams Haines - Boulder CO, US
James Joseph Touchton - Boulder CO, US
Assignee:
SEAGATE TECHNOLOGY LLC - Cupertino CA
International Classification:
G06F 12/00
US Classification:
711103, 711154, 711112, 711E12008
Abstract:
A method or system comprising iteratively updating a value of an operating parameter of a storage region of a storage device based on dynamic characterization of the storage region during operation of the storage device and using the updated value of the operating parameter during access to the storage region.
Non-Volatile Write Cache For A Data Storage System
US Patent:
8560770, Oct 15, 2013
Filed:
Nov 13, 2009
Appl. No.:
12/618268
Inventors:
Jonathan Williams Haines - Boulder CO, US
Brett Alan Cook - Westminster CO, US
Luke William Friendshuh - Elko MN, US
Mark Allen Gaertner - Vadnais Heights MN, US
Brett Alan Cook - Westminster CO, US
Luke William Friendshuh - Elko MN, US
Mark Allen Gaertner - Vadnais Heights MN, US
Assignee:
Seagate Technology LLC - Cupertino CA
International Classification:
G06F 12/00
US Classification:
711113, 711103, 711156, 711165, 711170, 36518533
Abstract:
The present disclosure provides a data storage system. In one example, the data storage system includes a data storage media component having a plurality of data storage locations. A first set of the plurality of data storage locations are allocated for a main data storage area. The data storage system also includes a controller configured to define a write cache for the main data storage area by selectively allocating a second set of the plurality of data storage locations.
Secure Erasure Of Data From A Non-Volatile Memory
US Patent:
2012027, Nov 1, 2012
Filed:
Apr 29, 2011
Appl. No.:
13/098093
Inventors:
Ryan James Goss - Prior Lake MN, US
David Scott Seekins - Shakopee MN, US
Jonathan W. Haines - Boulder CO, US
Timothy R. Feldman - Louisville CO, US
David Scott Seekins - Shakopee MN, US
Jonathan W. Haines - Boulder CO, US
Timothy R. Feldman - Louisville CO, US
Assignee:
SEAGATE TECHNOLOGY LLC - Scotts Valley CA
International Classification:
G06F 12/00
US Classification:
711155, 711E12001
Abstract:
Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained.
Multilevel Cell Memory Devices Having Reference Point Cells
US Patent:
7916537, Mar 29, 2011
Filed:
Jun 11, 2009
Appl. No.:
12/483038
Inventors:
Jonathan Williams Haines - Boulder CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G11C 16/00
US Classification:
36518503, 3651852, 3652101
Abstract:
Embodiments of the disclosure include multilevel memory cell devices that utilize reference point cells to determine the states of other cells. Embodiments of the disclosure also include methods of storing data to and retrieving data from multilevel memory cell devices utilizing reference point cells. In one embodiment, a multilevel memory cell device includes user data cells, a reference point cell, and a controller. The user data cells each has one of a plurality of states. The reference point cell has a first state. The controller determines the states of the user data cells based at least in part on the first state of the reference point cell.