Inventors:
Chau Chin Low - Freemont CA, US
Oscar Woo - Santa Cruz CA, US
Michael R. Fabry - Apple Valley MN, US
Terry A. Junge - Scotts Valley CA, US
Tiang Fee Yin - Singapore, SG
Choon An Aw - Singapore, SG
Jonathan E. Olson - Minneapolis MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H01L 2144, H01L 2148, H01L 2150, H01L 2128, H01L 213205
Abstract:
Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.