John William Petersen
Massage Therapy at Stuart St A304, Fort Collins, CO
License number
Colorado 2388
Issued Date
Apr 1, 2009
Renew Date
Feb 1, 2015
Expiration Date
Dec 31, 2016
Type
Massage Therapist
Address
Address
2960 W Stuart St, Fort Collins, CO 80526
Professional information
Microprocessor Design Manager
Position:
R&D Design Manager at Intel, Registered Patent Agent at Intel Corporation
Location:
Fort Collins, Colorado Area
Industry:
Computer Hardware
Work:
Intel
since Feb 2004
-
R&D Design Manager
Intel Corporation
- Fort Collins, CO since May 2005
-
Registered Patent Agent
Hewlett-Packard
May 1998 - Feb 2004
-
Microprocessor Design Engineer
Education:
Brigham Young University 1991 - 1998
Languages:
Tagalog
High Reliability Triple Redundant Latch With Integrated Testability
US Patent:
7095262, Aug 22, 2006
Filed:
Jul 19, 2004
Appl. No.:
10/894720
Inventors:
John T. Petersen - Fort Collins CO, US
Hassan Naser - Fort Collins CO, US
Jonathan P Lotz - Fort Collins CO, US
Hassan Naser - Fort Collins CO, US
Jonathan P Lotz - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, LP. - Houston TX
International Classification:
H03K 3/02
US Classification:
327197, 327198, 327199, 327200
Abstract:
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the second settable memory element, the third settable memory element and control to the settable memory elements determine the logical value held on the first settable memory element. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
High Reliability Triple Redundant Memory Element With Integrated Testability And Voting Structures On Each Latch
US Patent:
7027333, Apr 11, 2006
Filed:
Sep 3, 2004
Appl. No.:
10/934035
Inventors:
John T. Petersen - Fort Collins CO, US
Hassan Naser - Fort Collins CO, US
Jonathan P Lotz - Fort Collins CO, US
Hassan Naser - Fort Collins CO, US
Jonathan P Lotz - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C 7/10, G11C 11/00, G06F 11/08, H03K 5/22
US Classification:
36518905, 365 63, 365154, 36518908, 365194, 365206, 327 57, 327 64, 327 76, 714 6, 714797, 714820
Abstract:
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.
Soft-Error Rate Improvement In A Latch
US Patent:
7068088, Jun 27, 2006
Filed:
Oct 27, 2004
Appl. No.:
10/976034
Inventors:
John T. Petersen - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houson TX
International Classification:
H03K 3/356
US Classification:
327208, 327210, 327211
Abstract:
In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The input of a second inverter is connected to the output of the first inverter. When the input to the first inverter is disturbed by a soft error event, a signal tristates the first inverter.
John Petersen
Location:
Fort Collins, Colorado Area
Industry:
Computer Hardware