MR. JOHN WESLEY RILEY, L.M.T., M.T.I.
Massage Therapy at Bee Cave Rd, Austin, TX

License number
Texas MT003331
Category
Restorative Service Providers
Type
Massage Therapist
Address
Address
4407 Bee Cave Rd SUITE 513, Austin, TX 78746
Phone
(512) 732-0037
(512) 328-3228 (Fax)

Personal information

See more information about JOHN WESLEY RILEY at radaris.com
Name
Address
Phone
John Riley, age 57
5123 Kee Brook Dr, Arlington, TX 76017
(817) 313-6233
John Riley
504 N Parkway Dr, Alvarado, TX 76009
(817) 253-7585
John Riley
529 Bullingham Ln, Allen, TX 75002
(972) 670-5983
John Riley, age 51
5301 Paulie Dr, Denton, TX 76208
John Riley, age 49
519 Patchester Dr, Houston, TX 77079
(956) 498-7848

Professional information

John Aloysius Riley Photo 1

John Aloysius Riley, Austin TX - Lawyer

Address:
Bracewell & Giuliani LLP
111 Congress Ave STE 2300, Austin 78701
(512) 542-2108
Licenses:
Texas - Eligible To Practice In Texas 1987
Education:
Boston University School of LawDegree Doctor of Jurisprudence/Juris Doctor (J.D.)Graduated 1983
Boston University School of LawDegree J.D.Graduated 1983
Cornell UniversityDegree B.S.Graduated 1979
Specialties:
Licensing - 25%
Litigation - 25%
Government - 25%
Environmental / Natural Resources - 25%


John Riley Photo 2

General Manager At Jason's Deli

Position:
General Manager at Jason's Deli
Location:
Austin, Texas Area
Industry:
Restaurants
Work:
Jason's Deli since Sep 1998 - General Manager


John Riley Photo 3

Senior Design Engineer At Intel Corporation

Position:
Senior Design Engineer at Intel Corporation
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Intel Corporation - Senior Design Engineer


John Aloysius Riley Photo 4

John Aloysius Riley, Austin TX - Lawyer

Address:
Bracewell & Giuliani LLP
111 Congress Ave STE 2300, Austin 78701
(512) 542-8520
Licenses:
New York - Currently registered 1984
Education:
Boston University School of Law


John W Riley Photo 5

John W Riley, West Lake Hills TX - LMT

Specialties:
Massage Therapy
Address:
4407 Bee Caves Rd SUITE 513, West Lake Hills 78746
(512) 732-0037 (Phone), (512) 328-3228 (Fax)
Languages:
English


John Riley Photo 6

Methods And Systems To Improve Write Response Times Of Memory Cells

US Patent:
8068371, Nov 29, 2011
Filed:
Dec 31, 2008
Appl. No.:
12/347979
Inventors:
Feroze A. Merchant - Austin TX, US
John Reginald Riley - Austin TX, US
Vinod Sannareddy - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 7/10
US Classification:
36518904, 36518914, 36518908, 365196, 365100, 365148
Abstract:
Methods and systems to dynamically control state-retention strengths of a plurality of memory cells during a write operation to a subset of the memory cells. Dynamic control may include weakening state-retention strengths of the plurality of memory cells during a write operation to a subset of the memory cells, while preserving state-retention abilities of remaining ones of the plurality of memory cells. Weakening may include adjusting one or more resistances between one or more power supplies and the plurality of memory cells. Dynamic control may be selectively performed on portions of each of the memory cells in response to an input data logic state. Dynamic control may reduce a write contention within the subset of memory cells without disabling state-retention abilities of remaining ones of the plurality of memory cells, and may improve write response times of the memory cells.


John Riley Photo 7

Methods And Apparatuses For Operating Memory

US Patent:
7630228, Dec 8, 2009
Filed:
Aug 30, 2007
Appl. No.:
11/897442
Inventors:
John Reginald Riley - Austin TX, US
Mohammed Hasan Taufique - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 11/00
US Classification:
365154, 365226
Abstract:
In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply current controller to reduce current to at least a portion of the bit cell and to supply current to another portion of the cell in response to a write control signal and a data signal during a bit cell transition. Reducing the current to a portion of the bit cell and supplying current to another portion of the bit cell during transition can allow the bit cell to transition to a different state faster and can reduce the effects of device variations that manifest during low voltage operation. Other embodiments are also disclosed.