JOHN T NEILSON
Real Estate Commission in Norristown, PA

6856520, Feb 15, 2005

May 20, 2003

10/441033

John M. Neilson - Norristown PA, US
Francis J. Kub - Arnold MD, US
Karl D. Hobart - Upper Marboro MD, US

The United States of America as represented by the Secretary of the Navy - Washington DC

H02M003/335

363 16, 363 17

A double-side IGBT (DIGBT) phase leg architecture that uses the DIGBT as a substitute for a free wheeling diode to achieve reduced turn-on loss and reduced reverse recovery peak current during turn-on is described and characterized. Approximately a 50% reduction in reverse recovery peak current and an 80% reduction in recovery charge are achieved. In addition, low power dissipation (≈1 A current level) protection circuitry is described that can be incorporated into the DIGBT phase leg architecture to allow the flow of reverse current even if the gate driver circuit is disabled so that conventional high current free wheeling diodes are not required to provide protection.

6194290, Feb 27, 2001

Mar 9, 1998

9/037723

Francis J. Kub - Arnold MD
Victor Temple - Clifton Park NY
Karl Hobart - Upper Marlboro MD
John Neilson - Norristown PA

Intersil Corporation - Palm Bay FL

H01L 2130, H01L 2146, H01L 2144, H01L 2148, H01L 2150

438455

A method for making at least one semiconductor power device with current conduction in a vertical direction from a plurality of semiconductor substrates includes processing at least one surface of each of two semiconductor substrates to form at least one of a metal layer and a doped region. The substrates are bonded together so that the at least one processed surface of each of the two semiconductor substrates define outer surfaces of the semiconductor device. The method further includes annealing the bonded together substrates at an anneal temperature so as to not adversely effect the processed surfaces. The method allows the making of a double sided semiconductor power device with a reduction in the number of sequential processing steps. The direct bonding approach allows current production recipes for fabricating single sided power devices to be used without requiring a separate process sequence.

6274892, Aug 14, 2001

Mar 9, 1998

9/036838

Francis J. Kub - Arnold MD
Victor Temple - Clifton Park NY
Karl Hobart - Upper Marlboro MD
John Neilson - Norristown PA

Intersil Americas Inc. - Irvine CA

H01L 27082

257131

One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions. The localized lifetime killing portion may comprise a plurality of laterally confined and laterally spaced apart lifetime killing regions.

6153495, Nov 28, 2000

Mar 9, 1998

9/036815

Francis J. Kub - Arnold MD
Victor Temple - Clifton Park NY
Karl Hobart - Upper Marlboro MD
John Neilson - Norristown PA

Intersil Corporation - Palm Bay FL

H01L 2130

438459

A method for making a semiconductor device from a plurality of semiconductor substrates includes the steps of: processing at least one surface of at least one of the substrates; thinning at least one of the substrates; bonding the processed and thinned substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the at least one processed surface. The step of thinning preferably comprises removing a surface portion of the least one substrate opposite the processed surface, to a thickness of less than about 200. mu. m. A gettering layer may be formed for the at least one substrate prior to thinning. Accordingly, the step of thinning removes the gettering layer.