JOHN T GEHMAN
Broker in Needham, MA
License number
Massachusetts 9089897
Issued Date
Jun 8, 2006
Expiration Date
Feb 21, 2017
Type
Salesperson
Address
Address
Needham, MA 02492
Professional information
High-Speed Synchronous Computer Using Pipelined Registers And A Two-Level Fixed Priority Circuit
US Patent:
4310880, Jan 12, 1982
Filed:
Sep 10, 1979
Appl. No.:
6/073597
Inventors:
John T. Gehman - Needham MA
Assignee:
Nixdorf Computer Corporation - Burlington MA
International Classification:
G06F 938
US Classification:
364200
Abstract:
A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i. e. , the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.
Two-Level Priority Circuit
US Patent:
4443848, Apr 17, 1984
Filed:
May 4, 1981
Appl. No.:
6/260141
Inventors:
John T. Gehman - Needham MA
Assignee:
Nixdorf Computer Corporation - Burlington MA
International Classification:
G06F 938
US Classification:
364200
Abstract:
A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i. e. , the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.