John Rose Wilson
Residential Contractor at Oberlin Rd, Raleigh, NC

8068357, Nov 29, 2011

Sep 4, 2008

12/204728

Frederick Ware - Los Altos Hills CA, US
John Wilson - Raleigh NC, US
Jade M. Kizer - Durham NC, US
Lei Luo - Durham NC, US
John W. Poulton - Chapel Hill NC, US
Ian Shaeffer - Los Gatos CA, US

Rambus Inc. - Sunnyvale CA

G11C 5/06

365 63, 36518907, 36518909, 36518903

A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e. g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.

8198930, Jun 12, 2012

Oct 27, 2010

12/913754

Jared Zerbe - Woodside CA, US
Brian Leibowitz - San Francisco CA, US
Lei Luo - Durham NC, US
John Wilson - Raleigh NC, US
Anshuman Bhuyan - Stanford CA, US
Marko Aleksic - Mountain View CA, US

Rambus Inc. - Sunnyvale CA

H03H 11/26

327261, 327158, 327276

A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.

2011029, Dec 1, 2011

May 25, 2011

13/115838

Lei Luo - Durham NC, US
Brian S. Leibowitz - San Francisco CA, US
Jared L. Zerbe - Woodside CA, US
Barry W. Daly - Chapel Hill NC, US
Wayne D. Dettloff - Cary NC, US
John Wilson - Raleigh NC, US

H04L 27/00

375316

A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.

2013024, Sep 26, 2013

Jun 14, 2012

13/523631

Jared L. Zerbe - Woodside CA, US
Brian S. Leibowitz - San Francisco CA, US
Hsuan-Jung Su - Chapel Hill NC, US
Barry William Daly - Chapel Hill NC, US
Lei Luo - Durham NC, US
Teva J. Stone - Chapel Hill NC, US
John Wilson - Raleigh NC, US
Jihong Ren - Sunnyvale CA, US
Wayne D. Dettloff - Cary NC, US

RAMBUS INC. - Sunnyvale CA

H03L 7/00

327161, 327141

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

2006002, Feb 2, 2006

Aug 8, 2005

11/199341

Paul Franzon - Holly Springs NC, US
Stephen Mick - Apex NC, US
John Wilson - Raleigh NC, US

H01L 23/48

257734000

Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

7961003, Jun 14, 2011

Jul 30, 2010

12/847910

John Wilson - Raleigh NC, US

Rambus Inc. - Sunnyvale CA

H03K 17/16

326 30, 333124

A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point is coupled to a load impedance. The characteristic impedance of a line segment is matched to the equivalent impedance presented by the load impedance in combination with the characteristic impedance of a following segment, or is matched to the load impedance if there is no following segment.

8462891, Jun 11, 2013

Feb 19, 2009

12/920806

Jade M. Kizer - Windsor CO, US
John Wilson - Raleigh NC, US
Lei Luo - Durham NC, US
Frederick Ware - Los Altos Hills CA, US
Jared L. Zerbe - Woodside CA, US

Rambus Inc. - Sunnyvale CA

H04L 27/06

375340, 375257, 375264, 375286, 375288, 375295, 375316, 375318, 341 55, 341 56, 341143

Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

8451913, May 28, 2013

Dec 17, 2010

12/971213

Kyung Suk Oh - Cupertino CA, US
John Wilson - Raleigh NC, US
Jihong Ren - Sunnyvale CA, US

Rambus Inc. - Sunnyvale CA

H04B 3/00, H04L 25/00

375257

A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise.

8451674, May 28, 2013

Apr 13, 2012

13/446703

Jade M. Kizer - Windsor CO, US
John M. Wilson - Raleigh NC, US
John Eble, III - Chapel Hill NC, US
Frederick A. Ware - Los Altos Hills CA, US

Rambus, Inc. - Los Altos CA

G11C 7/00

365193, 3652331, 36523006

Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.