John Robert McBride
Engineers at Rochdale Dr, Fort Collins, CO

6507807, Jan 14, 2003

Aug 13, 1999

09/373682

John G McBride - Ft Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 944

703 14, 703 17, 716 4, 716 6, 716 5

The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the total effective RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network. In accordance with the preferred embodiment of the present invention, the rules checker algorithm performs these tasks by: (1) analyzing each branch of the network to determine the primary RC delay of each branch assuming the branch being analyzed corresponds to the worst case RC delay of the network; (2) analyzing each branch of the network assuming one of the other branches of the network corresponds to the worst case RC delay of the network and determining the effect that the resistances and capacitances of the branch being analyzed would have on other branches; (3) determining the total effective RC delay of each branch by combining the primary RC delay of each branch with the effect that the other branches have on the branch being analyzed; and (4) determining which branch of the network has the largest total effective RC delay.

6701290, Mar 2, 2004

Feb 18, 1999

09/252950

John G McBride - Ft Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1750

703 15, 703 14, 703 13, 716 4

A method and apparatus for evaluating an integrated circuit design to determine whether a pass FET is part of a RAM cell structure in the integrated circuit design. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a pass FET in the integrated circuit is part of a RAM cell structure of the integrated circuit. The rules checker program of the present invention evaluates each pass FET which is channel-connected at one of its terminals to a latch node and determines whether that pass FET is channel-connected at one of its other terminals to the drain or source terminal of at least one other pass FET. If so, the pass FET being evaluated is part of a RAM cell structure. In accordance with the preferred embodiment of the present invention, the rules checker program evaluates nodes in an integrated circuit to detect latch nodes.

6523152, Feb 18, 2003

Mar 8, 2000

09/521866

Ted Scott Rakel - Fort Collins CO
John G McBride - Ft Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1750

716 5, 716 4, 716 6

An Electrical Rules Check (ERC) methodology ensures the quality of an electrical circuit through the creation of up to four different data structures, corresponding to one or more nodes, one or more small nodes, one or more non-resistor elements, and one or more resistor elements of the circuit, that are used by an ERC program running on one or more processors. The creation of data structures for small nodes and resistor elements in which less information need be stored for use by the ERC program minimizes the amount of data storage that must be utilized.

6542860, Apr 1, 2003

Mar 22, 1999

09/273783

John G McBride - Ft Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1750

703 14, 703 2, 716 5, 716 6

The present invention is generally directed to a system and method for identifying nodes in a circuit design that are susceptible to floating. In accordance with one aspect of the invention, a method identifies nodes susceptible to floating by first detecting a node that is an output of a pass gate. The method then evaluates the circuit structure surrounding the node to ensure that the surrounding circuit structure is not one of several permissible structures. In this regard, the method ensures that the node is not an output node of a static gate. It also determines that the node is not an output of a multiplexer. If further verifies that the node is not an output of a pass gate that is always on. In addition, the method determines that the node drives a FET gate. In accordance with another aspect a computer readable storage medium, containing program code for evaluating a netlist, may be provided to detect a node that is susceptible to floating comprising.

6718522, Apr 6, 2004

Aug 15, 2000

09/639613

John G McBride - Ft Collins CO
Jan Kok - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1750

716 4, 716 5

An electrical rules checker system and method are provided to identify tri-state logic from a netlist. In accordance with one aspect of the invention, a method identifies tri-state logic from a netlist by selecting a circuit configuration to be identified, and then identifying any of the circuit configurations at the node, and identifyng any probable circuit configurations at the node. In accordance with another aspect of the invention, a system is provided for identifying tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist.

6321365, Nov 20, 2001

Jan 26, 1999

9/236893

John G McBride - Ft Collins CO

Hewlett-Packard Company - Palo Alto CA

C06F 1700

716 5

The present invention is generally directed to a system and method for identifying a storage node that is susceptible to charge sharing by another node. In accordance with one aspect of the invention, a method identifies storage nodes susceptible to charge sharing by first identifying, from a netlist, a storage node. For a given storage node, the method determines whether any pass FET devices are being driven by the storage node. For any such pass FET devices, the method retrieves a capacitance value for both sides of the pass FET devices being driven by the storage node. Specifically, a first capacitance value is retrieved for the storage node side of each pass FET device, and a second capacitance value is retrieved for a node on the opposite side of each pass FET device. Then the method calculates a ratio between the first and second capacitance values for each pass FET device being driven by the storage node. Finally, the method compares this ratio to a predetermined value, and generates a warning message if the ratio is greater than the predetermined value No.

7031889, Apr 18, 2006

Mar 22, 1999

09/273784

John G McBride - Ft Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 17/50

703 2, 703 13, 716 5

A method and apparatus for evaluating the design quality of an integrated circuit design. The design to be evaluated comprises a plurality of static gates, such as, for example, NAND and NOR gates. The apparatus of the present invention comprises a computer configured to execute a rules checker program. The rules checker program analyzes each of the static gates to determine whether or not the gates meet acceptable noise immunity requirements. In order to perform this task, the rules checker program constructs models of each gate. The models emphasize or de-emphasize the strengths of certain FETs of the gate in response to noise on inputs to the gate for different logic states of the inputs. For each model, the rules checker program obtains a PFET-to-NFET width ratio. These ratios are utilized to obtain noise levels from a lookup table.

6275970, Aug 14, 2001

Feb 18, 1999

9/252378

John G McBride - Ft Collins CO

Hewlett Packard Company - Palo Alto CA

G06F 1750, G06F 738, H01L 2500

716 4

A method and apparatus for detecting a predischarge node in an integrated circuit. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a predischarge node exists in the integrated circuit. The rules checker program evaluates each node in the integrated circuit and determines whether or not an N field effect transistor (NFET) is connected to the node and, if so, whether the gate terminal of the NFET is connected to a clock and whether a drain or source terminal of the NFET is connected to ground. The rules checker program also determines whether or not a P field effect transistor (PFET) is connected to the node being evaluated and, if so, whether it has a gate terminal which is not connected to a clock and drain and source terminals which are not connected to a supply. If all of these conditions are true, the rules checker program determines that the node being evaluated is a predischarge node.

5987237, Nov 16, 1999

Sep 2, 1997

8/922793

John G. McBride - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 9455

39550001

A rules checking methodology ensures the quality of a structure or system having one or more elements and one or more nodes that serve as connection points to the elements. The rules checking methodology examines the elements and nodes of the structure and makes decisions regarding the quality of the structure according to parameters, or rules, provided.