JOHN RICHARDS, MD
Medical Practice in San Jose, CA

6349079, Feb 19, 2002

Oct 8, 1999

09/414745

Karl A. Belser - San Jose CA
Lawrence M. Bryant - Palo Alto CA
John H. Richards - San Jose CA

Seagate Technology LLC - Scotts Valley CA

G11B 700

369 4426, 369 4434, 369 5328

A system and method are provided for processing signals in a magneto-optical computer memory device to detect mispositioning of a head with respect to a track centerline. A light beam is scanned over a first and a second set of radially offset optically-detectable position marks formed in the rotating medium surface. A detector receives the reflected light beam and responsively generates a position signal having a plurality of pulses corresponding to the position marks. The position signal is then passed through a differentiator circuit. The differentiated position signal may then be applied to low pass filter and resonator circuits, and is subsequently conveyed to a finite time integrator for rectification and detection of the areas of the pulses associated with the first and second set of position marks. Mispositioning of the head is detected by comparing the pulse areas of the first and second set of position marks.

5333138, Jul 26, 1994

Mar 11, 1992

7/849740

John H. Richards - San Jose CA
Karl D. Schuh - San Jose CA

MiniStor Peripherals International Limited - San Jose CA

G06F 1100, G11B 1504

371 7

Apparatus for preventing data corruption on a disk due to mechanical shock occurring during the write process to the disk includes a mechanical shock sensor to sense mechanical shocks having a magnitude exceeding a predetermined threshold. Write disable circuitry responsive to the mechanical shock sensor interrupts the write current to the disk drive write head. Repositioning circuitry then repositions the data head over the original data track and the incomplete data that was interrupted by the mechanical shock is rewritten. A method for preventing data corruption on a disk due to mechanical shock experienced by a disk drive during the write process to the disk includes the steps of sensing a mechanical shock having a magnitude exceeding a predetermined threshold; storing information identifying the data being written at the onset of the sensed shock; interrupting the write current to the write head; repositioning the data head to the original track; and rewriting the data which was interrupted because of the sensed shock.

5444009, Aug 22, 1995

Dec 23, 1994

8/363733

John G. Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA

Micro Technology Partners - San Jose CA

H01L 2900

437 51

An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure. A substantially planar first metallic pad is provided for a first connection to external circuitry.

5557149, Sep 17, 1996

Mar 24, 1995

8/409994

John G. Richards - San Jose CA
Wendell B. Sander - Los Gatos CA
Donald P. Richmond - Palo Alto CA
Hector Flores - San Jose CA

ChipScale, Inc. - San Jose CA

H01L 2348, H01L 2352

257779

A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the second side of the wafer such that a portion of the first layer becomes exposed in the trench. A second layer having a second material is formed over the second side of the wafer such that a portion of the second layer contacts the portion of the first layer exposed in the trench. The wafer is separated through the trench. The trench may be formed by sawing the second side of the wafer in an area where the trench is to be formed. The wafer may then be etched such that the trench is formed.

5455187, Oct 3, 1995

Nov 1, 1994

8/331783

John G. Richards - San Jose CA
Hector Flores - San Jose CA

Micro Technology Partners - San Jose CA

H01L 21302, H01L 2144, H01L 2148, H01L 2176

437 62

An electrical apparatus having a first substrate, a first metallic layer, a semiconductor device, a second metallic layer, and a metallic interconnecting structure is described. The first substrate is of a semiconductor material and has an upper region and a lower region. The substrate provides an electrical path between the upper region and the lower region. The first metallic layer is coupled to the lower region of the substrate. The first metallic layer provides a first external electrical connection. The semiconductor device has an upper region and a lower region. The second metallic layer is coupled to the lower region of the semiconductor device. The second metallic layer provides a second external electrical connection. The metallic interconnecting structure electrically couples the upper region of the first substrate to the upper region of the semiconductor device. A bridge apparatus is also described.

5521420, May 28, 1996

Jul 5, 1994

8/270784

John G. Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA

Micro Technology Partners - San Jose CA

H01L 2348, H01L 2946, H01L 2952

257735

An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure. A substantially planar first metallic pad is provided for a first connection to external circuitry.

5656547, Aug 12, 1997

May 11, 1994

8/241602

John G. Richards - San Jose CA
Wendell B. Sander - Los Gatos CA
Donald P. Richmond - Palo Alto CA
Hector Flores - San Jose CA

ChipScale, Inc. - San Jose CA

H01L 2158, H01L 2352, H01L 2170

438460

A flange interface for wrap-around contact regions formed in fabricating semiconductor devices provides for a durable and reliable electrical bond. A first layer having a first material is formed over the first side of a wafer. A trench is formed from the second side of the wafer such that a portion of the first layer becomes exposed in the trench. A second layer having a second material is formed over the second side of the wafer such that a portion of the second layer contacts the portion of the first layer exposed in the trench. The wafer is separated through the trench. The trench may be formed by sawing the second side of the wafer in an area where the trench is to be formed. The wafer may then be etched such that the trench is formed.

4738933, Apr 19, 1988

Aug 27, 1985

6/769911

John G. Richards - San Jose CA

FEI Microwave, Inc. - Sunnyvale CA

H01L 2104

437 15

A monolithic semiconductor device that provides a diode having PIN diode characteristics. The diode has anode and cathode mesas having contacts in substantially the same plane to facilitate automatic bonding. One of the contacts is insulated from its associated mesa and has a conductive layer that extends between the mesas and through an insulating layer to make direct contact with the substrate, thereby isolating the flow of current from any intervening I regions. The conductive layer may include a portion of narrow cross section, to function as a fuse.

4746398, May 24, 1988

Jun 18, 1987

7/063376

Hormoz M. Motamedi - San Jose CA
John G. Richards - San Jose CA
Hector H. Flores - San Jose CA

FEI Microwave, Inc. - Sunnyvale CA

B44C 122, H01L 2158, H01L 2160, C03C 1500

156644

A gallium arsenide tunnel diode is fabricated using planar techniques from a wafer of gallium arsenide that has been heavily doped to form a P region. Tin is plated onto an exposed section of a surface of the wafer and then melted to cause individual tin atoms to diffuse only a few atomic layers into the wafer, creating a heavily doped N region. Metal contact layers are then formed over the tin and on the opposite surface of the wafer. An oxidation inhibitor is used during the plating and a scavenging agent is used during the melting to insure intimate contact between the tin and the wafer.