JOHN MORRIS
Electrician at Ashford Pt Dr, Houston, TX

5568493, Oct 22, 1996

Mar 17, 1995

8/405740

John O. Morris - Houston TX

Texas Instruments Incorporated - Dallas TX

G01R 3127

371 223

An integrated circuit containing analogue operation circuitry having a plurality of nodes for input and output of signals during normal operation, a plurality of scan cells connected to at least said plurality of nodes for containing signals to be utilized in selected tests to be performed on said analogue operation circuitry and responsive to selected output signals is provided. A method for testing a module of analogue circuitry incorporated into an integrated circuit having other circuitry by decoupling a plurality of module signal terminals from respective normal operation connections to a plurality of scan cells, and inputting at least portions of test suites and sensing test result output signals through at least selected ones of said scan cells is provided.

5386533, Jan 31, 1995

Nov 21, 1990

7/616521

John O. Morris - Houston TX

Texas Instruments Incorporated - Dallas TX

G06F 1202

395425

An apparatus and method for maintaining variable data in a non-volatile electronic memory device comprises a shifter array (106) which provides a shifter value to shifter register (104). Shifter register (104) uses 8-bit column decoder (110) to specify which of a plurality of overlapping storage units in array (94) will store variable data provided from register (92). Address register (112) specifies to row decoder (116) which of two rows in shifter array (106), pointer array (118) and array (94) will be accessed by read and write operations. Pointer array (118) stores an index specifying which of the two rows contains the most recently updated variable data. Shifter register (104) uses 8-bit column decoder (108) to specify which of a plurality of adjacent storage units in pointer array (118) will store the index. OR gate (98) specifies when to replace an overlapping storage unit in array (94) and an adjacent storage unit in pointer array (118).

5315553, May 24, 1994

Jun 10, 1991

7/712793

John O. Morris - Houston TX

Texas Instruments Incorporated - Dallas TX

G11C 700

365201

A memory test method and system are described which comprises a first memory array and a second memory array coupled to a plurality of row address lines within a memory system. During the testing of the memory system, row decode logic is used to sequentially access each of the row address lines The second memory array stores a predetermined value associated with each of the row address lines. Accordingly, accuracy of the row decode logic and continuity of the row address lines can be verified without the necessity of programming each memory location within the first memory array.