JOHN MICHAEL PORTER
Pilots at Rockcliff Rd, Austin, TX

5268866, Dec 7, 1993

Mar 2, 1992

7/844022

Stephen T. Flannagan - Austin TX
John D. Porter - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 700

365200

A memory (20) has a plurality of columns of memory cells and has a plurality of redundant columns of memory cells. A comparator (45) detects an access to a defective column. A redundant write generator (31) and write fuses (32) are provided for each write portion (30A, 30B, 30C, and 30D) to replace the defective column with a redundant column by replacing a write global data line (37) with a redundant write global data line (39). Redundant read generators (60 and 61) and read fuses (59) are provided for each read portion (50A, 50B, 50C, and 50D) to replace a defective column by deselecting a read global data line (29) and replacing it with a redundant read global data line (44). The fuses and redundant generators are located close to their global data lines, thus reducing the routing of control signals and improving the access time of redundant columns.

5291455, Mar 1, 1994

May 8, 1992

7/880381

Taisheng Feng - Austin TX
John D. Porter - Austin TX
Jennifer Y. Chiao - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 514

365226

A memory (20) has N. sub. BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V. sub. CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V. sub. AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V. sub. AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.

5687178, Nov 11, 1997

Mar 25, 1996

8/621370

Lawrence Norman Herr - Coupland TX
John David Porter - Austin TX
Mary Ann Coones - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 2900

371 214

A method and apparatus for testing a static RAM includes a word line voltage control circuit (42) and an array supply voltage control circuit (46). In response to receiving a first control signal from a tester, the word line voltage control circuit (42) is used to provide a word line voltage to each word line of the memory array (31). The array supply voltage control circuit (46) provides a supply voltage to the array (31) in response to receiving a second control signal from the tester. During testing of memory 30, the array supply voltage and the word line voltage are supplied independently of the memory power supply voltage V. sub. DD in order to quickly detect memory cells that are defective due to soft defects.

5256917, Oct 26, 1993

Apr 3, 1992

7/863623

Stephen T. Flannagan - Austin TX
John D. Porter - Austin TX

Motorola, Inc. - Schaumburg IL

H03K 19003, H03K 19086, H03K 190175

307455

An ECL logic gate (70) includes a voltage protection clamp (60) for protecting a first bipolar transistor (58) from being too heavily reverse biased when an input signal A. sub. IN is pulled to V. sub. SS. The ECL logic gate (70) includes an emitter-follower input stage and a differential amplifier stage. A voltage protection clamp (60) includes a second transistor (52) and a resistor (53) and acts to divide the amount of reverse bias on the first bipolar transistor (58) between a third transistor (51) and the first transistor (58), thereby bringing the reverse bias voltage on the first transistor (58) within acceptable levels to prevent degradation of the first transistor (58).

5003513, Mar 26, 1991

Apr 23, 1990

7/513126

John D. Porter - Austin TX
Brian D. Branson - Austin TX

Motorola, Inc. - Schaumburg IL

G11C 1141

36523008

An ATD memory has an input buffer which latches addresses while maintaining good D. C. margin, hysteresis, and transition detection. The input buffer includes two input circuits for receiving the address. A transmission-gate type latch is used to latch the outputs of the two input circuits. An internal buffer circuit receives the output of the latch and provides internal address signals useful to a decoder in selecting a memory cell. The internal buffer circuit also provides slow and fast signals useful in performing transition detection. The latch either provides outputs responsive to the address signal or an output representative of the address signal at the time a latch enable signal is received.

5343428, Aug 30, 1994

Oct 5, 1992

7/956230

Harold Pilo - Austin TX
John D. Porter - Austin TX

Motorola Inc. - Schaumburg IL

G11C 700

36518905

A memory (80) having a latching BICMOS sense amplifier (20) includes a reduced power data retention mode. The latching BICMOS sense amplifier (20) senses and amplifies differential data signals corresponding to data from a selected memory cell (85). A latch (35) temporarily retains the logic state of the differential data signals in response to a clock signal. The reduced power data retention mode is provided by utilizing selectable current sources (66-75) responsive to an output enable signal. The latching BICMOS sense amplifier (20) allows for very high speed operation, yet provides for reduced power consumption while in a latched state.