JOHN MARC PRICKETT
Pilots at Whitetail Dr, Manchaca, TX
License number
Texas A1529185
Issued Date
Jul 2016
Expiration Date
Jul 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
501 Whitetail Dr, Manchaca, TX 78652
Professional information
Trace On/Off With Breakpoint Register
US Patent:
6145123, Nov 7, 2000
Filed:
Jul 1, 1998
Appl. No.:
9/108531
Inventors:
James M. Torrey - Austin TX
John M. Prickett - Manchaca TX
Jim L. Lloyd - Austin TX
John M. Prickett - Manchaca TX
Jim L. Lloyd - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 9445
US Classification:
717 4
Abstract:
An information processing system such as a microprocessor includes a processor core, a debug register circuit and a trace unit. The processor core is for processing information according to a program. The program includes a plurality of instructions for execution by the processor core. Each of the plurality of instructions has a corresponding address. The debug register circuit is coupled to the processor core. The debug register circuit includes a dedicated initiate trace breakpoint register coupled to receive and store an initiate trace address and a dedicated terminate trace breakpoint register coupled to receive and store a terminate trace address. The trace unit is coupled to the debug register circuit and the processor core. The trace unit initiates a program trace responsive to the program accessing the initiate trace address. The trace unit terminates the program trace responsive to the program accessing the terminate trace address.
Failsafe Asynchronous Data Transfer Corruption Indicator
US Patent:
6195769, Feb 27, 2001
Filed:
Jun 26, 1998
Appl. No.:
9/105541
Inventors:
John M. Prickett - Manchaca TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1342
US Classification:
714 49
Abstract:
A data corruption indicator circuit for providing error free data transfer between a first device and a second device, clocked by different clock signals, is implemented. The data corruption indicator circuit can allow for faster throughput than the described prior art and provides a circuitry for detecting corrupt data. The data corruption indicator circuit provides a clocked data ready signal that updates a status lip-flop and a delayed data ready signal that updates a plurality of data flip-flops and a potential corruption flip-flop. Additionally, the delayed data ready signal may be used as an interrupt signal to notify the second device that data is available for transfer. The delay between the clocked data ready signal and the delayed data ready signal is such that a hazard cannot exist for the data signal and the status signal simultaneously. The failsafe nature of the invention is that while the status signal may indicate corrupt data when the data is actually valid, it will not indicate valid data when the data is corrupt.