JOHN LARRY THOMPSON, LCSW
Social Work at Hope Rd, Tinton Falls, NJ

4598358, Jul 1, 1986

Oct 29, 1982

6/437544

James R. Boddie - Hazlet NJ
Renato N. Gadenz - Tinton Falls NJ
John S. Thompson - Tinton Falls NJ

AT&T Bell Laboratories - Murray Hill NJ

G06F 936

364200

A pipelined digital signal processor includes a common data and control bus (101) and a source (100,105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-L,M,N and IR-S,T) receive a single instruction (i. e. , I. sub. i) during each processor cycle for controlling all processing subsections (112, 115, 116) operations. During each processor cycle, each processing subsection (i. e. , 112) performs an operation relating to a different expression than the other processing subsections (i. e. , 115 or 116) are performing during that processor cycle. All of the operations controlled by the single instruction (i. e. , I. sub.

4539635, Sep 3, 1985

Jul 23, 1982

6/401350

James R. Boddie - Hazlet NJ
John S. Thompson - Tinton Falls NJ

AT&T Bell Laboratories - Murray Hill NJ

G06F 738

364200

A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 116) performing operations according to an expression, thereby producing a resultant data word and a status signal. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i. e. , i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i. e. , i+3). A circuit (215 and 122) compares the status signal with the specific condition information included in the conditional instruction for selectively disabling at least one section while enabling at least one other section of the digital processor during the second subsequent processor cycle.

4072830, Feb 7, 1978

Oct 4, 1976

5/729004

Richard D. Gitlin - Monmouth Beach NJ
John S. Thompson - Tinton Falls NJ

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

H04B 324

1791702

The echo path of an echo signal subjected to a time-varying phase shift is bridged by echo cancelling apparatus including a variable phase shifter and an adaptive echo canceller connected in series. The variable phase shifter includes an adaptive control loop whose operation is compatible with that of an adaptive echo canceller. The phase-shifter control loop derives a control signal from the output signal synthesized by the echo cancelling apparatus and the residual echo produced by subtracting this output signal from the echo path signal. The control signal is used to produce a variable phase shift on the signal passing through the variable phase shifter in the echo cancelling apparatus. The echo canceller adaptively synthesizes a replica of the echo signal produced by the linear dispersive portion of the echo channel, while the variable phase shifter is adapted to impart a time-varying phase shift corresponding to the time-varying phase shift encountered by the echo signal in the echo path. The echo cancelling apparatus is therefore able to produce an output signal which closely approximates the echo signal including the time-varying phase shift for more effective echo cancellation.

4057696, Nov 8, 1977

Aug 9, 1976

5/712518

Richard Dennis Gitlin - Monmouth Beach NJ
John Stewart Thompson - Tinton Falls NJ

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

H04B 320

1791702

The circuit complexity of a closed-loop echo cancellation system for use in a two-way communication circuit is reduced by employing a second adjustable signal processing network of the transversal type positioned in the control loop to emulate the characteristic of a recursive adjustable signal processing network. The two signal processing networks in the control loop are adjusted simultaneously to effect echo cancellation. The second signal processing network compensates for the effect of transmission poles in the echo return path and reduces the duration of the impulse response of the echo return path significantly so that the first signal processing network in the control loop is greatly simplified. A third signal processing network of the recursive type is adjusted in accordance with the internal settings of the second network to perform signal processing inverse to that of the second network. The recursive network is utilized to provide a clear signal path through the echo cancellation system which is essentially free of echo.

4503490, Mar 5, 1985

Jun 10, 1981

6/272300

John S. Thompson - Tinton Falls NJ

AT&T Bell Laboratories - Murray Hill NJ

G06F 104

364200

A timing system, for distributing clock signals in a synchronous processing system having plural processing sections, includes a central clock circuit and a plurality of section clock circuits, each section clock circuit being located in and associated with a different one of the processing sections. Each section clock circuit is arranged to respond to a system clock signal for stepping through a plurality of states including a state common to the plurality of section clock circuits. An arrangement, responsive to the system clock signal, produces and transmits to the plurality of section clock circuits a synchronization signal that routinely sets the plurality of section clock circuits to the common state. The timing system may further include an arrangement for controlling suspension of processing in the plural processing sections.