JOHN JOSEPH ZASIO
Pilots at Lennox Way, Sunnyvale, CA

3981070, Sep 21, 1976

Jul 24, 1974

5/491237

Fred K. Buelow - Los Altos CA
John J. Zasio - Sunnyvale CA

Amdahl Corporation - Sunnyvale CA

B01J 1700

29574

LSI chip construction having a semiconductor body with a plurality of transistors formed in the semiconductor body in a predetermined pattern and a plurality of resistors formed in a semiconductor body in a predetermined pattern. Means is provided which includes two layers of metallization having input and output pads adjacent the outer perimeter of the body and contacting said transistors and resistors to form a plurality of emitter-follower circuits with certain of the emitter-follower circuits being made up of larger transistors and being located near the perimeter of the chip and near the input-output pads. The other emitter coupled circuits are clustered in groups to form an array of such groups with each of the groups being capable of containing a plurality of logic circuits.

6337576, Jan 8, 2002

Jul 19, 1999

09/357481

Andrew K. Wiggin - Campbell CA
Allan Calamoneri - Danville CA
Martin P. Goetz - Discovery Bay CA
John Zasio - Sunnyvale CA
George E. Avery - Saratoga CA
Sammy K. Brown - Los Gatos CA

Alpine Microsystems, Inc. - Campbell CA

G01R 3102

324763, 361761

A method and a system for wafer level burn-in testing of a circuit featuring a flip-jumper to permit selectively connecting signals to the interconnect sites on the wafer that are in constant electrical communication with the circuit.

6300161, Oct 9, 2001

Feb 15, 2000

9/504061

Martin P. Goetz - Discovery Bay CA
John Zasio - Sunnyvale CA

Alpine Microsystems, Inc. - Campbell CA

H01L 2144, H01L 2900

438106

A module and method for interconnecting integrated circuits. The module includes an insulative body that features conductive traces having differing resistivities associated therewith. To that end, the insulative body has, disposed therein, a conductive bond pad and a plurality of spaced apart conductive traces, one of which is in electrical communication with the bond pad, with each of the plurality of conductive traces are formed from a material having a resistivity associated therewith. The resistivity of the material from which one of the plurality of conductive traces is formed being greater than the resistivity of the material from which the remaining conductive traces are formed and defines a decoupling capacitor therebetween.

4495628, Jan 22, 1985

Jun 17, 1982

6/389573

John J. Zasio - Sunnyvale CA

Storage Technology Partners - Louisville CO

G11C 1928

377 70

A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

4495629, Jan 22, 1985

Jan 25, 1983

6/460952

John J. Zasio - Sunnyvale CA
Larry Cooke - Cupertino CA

Storage Technology Partners - Louisville CO

G11C 1128

377 70

An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit. When operating as a shift register circuit, shift-in data is coupled to the second latch element, and this second latch element operates as the "master" and the third latch element operates as the "slave" of a master/slave latch through which data is selectively shifted by appropriate clock signals.

5095356, Mar 10, 1992

Oct 9, 1990

7/594309

Hisashige Ando - Santa Clara CA
Hung C. Lai - Cupertino CA
John J. Zasio - Sunnyvale CA

Fujitsu Limited - Kawasaki

H01L 2710, H01L 2702

357 45

Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurality of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells.

4132898, Jan 2, 1979

Nov 1, 1977

5/847476

Fred K. Buelow - Los Altos Hills CA
John J. Zasio - Sunnyvale CA
Laurence H. Cooke - Cupertino CA

Fujitsu Limited - Kawasaki

A61K 2702

250492A

An electron beam exposure apparatus and method for use in fabricating semiconductor devices. A chip pattern larger in area than the electron beam scan field is divided into and exposed in a number of smaller parts (called partitions). The work piece on which the chip pattern is to be formed is moved relative to the scan field to enable each partition to be individually scanned at a different work piece position. The scan field, with the work piece positioned to scan one partition, overlaps onto and establishes a boundary region on an adjacent partition. Portions of chip patterns which lie in a boundary region are selectively scanned in connection with one or another of the abutting partitions. Portions of chip patterns falling in the boundary regions are selected for scanning in one or the other of adjacent partitions so as to minimize the number of divisions and so as to avoid dividing the pattern along critical dimensions.

4147937, Apr 3, 1979

Nov 1, 1977

5/847485

Fred K. Buelow - Los Altos Hills CA
John J. Zasio - Sunnyvale CA
Laurence H. Cooke - Cupertino CA

Fujitsu Limited - Kawasaki

A61K 2702

250492A

An electron beam exposure system and method for use in the process of fabricating microminiature devices at high speeds. The high-speed operation is achieved with a computer providing programmed commands specifying a particular pattern to be scanned. A processor, responsive to programmed data, generates scan data a line at a time and loads a line generator. The line generator steps to each exposure location in a line to provide control signals for controlling the position of the electron beam. The starting and end positions of scan lines in both the X and Y directions may be arbitrarily selected thereby eliminating the need for scanning areas not intended to be processed.

4924430, May 8, 1990

Jan 28, 1988

7/149555

John J. Zasio - Sunnyvale CA
Kenneth C. Choy - Fremont CA
Darrell R. Parham - Sunnyvale CA

Teradyne, Inc. - Boston MA

G06F 1560, G06F 1100

364578

The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

4937770, Jun 26, 1990

Dec 29, 1988

7/292620

Michael W. Samuels - San Jose CA
John J. Zasio - Sunnyvale CA

Teradyne, Inc. - Boston MA

G06G 748, G11C 700

364578

A levelized simulation system includes a means for storing a model of a logic system to be simulated. The logic system has a plurality of levels of logic which are synchronously clocked. A processing system including an arithmetic logic unit sequentially tests each element of said logic system, one level of logic at a time, thus each logic element in the first level is tested with the results there stored in a state memory, after which the logic elements of the second level of the logic system are tested and so on. During each test a comparison is made to determine whether there is a defect in the logic design.