John Joseph Foley
Architects at Wanstraw Way, Apex, NC
License number
North Carolina 4864
Category
Architecture
Address
Address
8412 Wanstraw Way, Apex, NC 27539
Professional information
Synchronizing Media Data From Multiple Data Channels For Ip Network Transport
US Patent:
8503483, Aug 6, 2013
Filed:
May 4, 2007
Appl. No.:
11/797556
Inventors:
John Andrew Foley - Apex NC, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04J 3/06
US Classification:
370503, 370476, 370352
Abstract:
In one embodiment, a method comprises receiving by a gateway a plurality of data streams via respective data channels; identifying by the gateway, from among the data streams, selected data streams for aggregation based on the selected data streams each having a same encoding type and destined for a same destination gateway; and synchronizing the selected data streams by the gateway based on: successively sampling a prescribed group of bits from each of the selected data streams at a corresponding sampling time interval, aggregating the sampled groups of bits, having been sampled from the selected data streams at the corresponding sampling time interval, into an IP media packet payload, and outputting a corresponding IP media packet, containing the IP media packet payload for the corresponding sampling time interval, to the destination gateway via an IP network.
Adaptive Memory Scrub Rate
US Patent:
8255772, Aug 28, 2012
Filed:
Jun 18, 2008
Appl. No.:
12/214283
Inventors:
John A. Foley - Apex NC, US
Assignee:
CISCO TECHNOLOGY, Inc. - San Jose CA
International Classification:
G11C 29/42, G11C 29/54
US Classification:
714764, 714718
Abstract:
In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e. g. , bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.
Adaptive Memory Scrub Rate
US Patent:
8443262, May 14, 2013
Filed:
Jul 17, 2012
Appl. No.:
13/551451
Inventors:
John A. Foley - Apex NC, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G11C 29/42, G11C 29/54
US Classification:
714764, 714718
Abstract:
In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e. g. , bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.
Processor Reliability Improvement Using Automatic Hardware Disablement
US Patent:
8230286, Jul 24, 2012
Filed:
Jun 16, 2009
Appl. No.:
12/485517
Inventors:
John Foley - Apex NC, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G01R 31/28
US Classification:
714736, 714 44
Abstract:
Techniques are provided herein to dynamically disable a hardware component in a processor device. Notifications for single-bit errors detected in a hardware component are received. The hardware component is disabled for a period of time when a number of single-bit errors exceeds a threshold. In addition, techniques are provided to permanently disable one or more hardware components in order to minimize the number of system malfunctions associated with single event upsets (SEUs).