JOHN FREDERICK ROBINSON
Pilots at Chicon St, Austin, TX
License number
Texas C1080343
Category
Airmen
Address
Address
1703 Chicon St, Austin, TX 78702
Professional information
President, Capitol Services, Inc.
Position:
President at Capitol Services, Inc.
Location:
Austin, Texas Area
Industry:
Legal Services
Work:
Capitol Services, Inc.
since 1978
-
President
Texas Comptroller of Public Accounts
1980 - 1982
-
Director of Budget & Research
National Bank of Commerce, Dallas, TX
1970 - 1975
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Vice President
Education:
The University of Texas School of Law 1975 - 1977
J.D., Law The University of Texas at Austin 1967 - 1968
MBA, Management & Finance The University of Texas at Austin 1962 - 1967
BBA, Management
J.D., Law The University of Texas at Austin 1967 - 1968
MBA, Management & Finance The University of Texas at Austin 1962 - 1967
BBA, Management
C. Aubrey Smith Professor Of Accounting At University Of Texas - Pan American
Position:
C. Aubrey Smith Professor of Accounting at University of Texas - Pan American
Location:
Austin, Texas Area
Industry:
Education Management
Work:
University of Texas - Pan American
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C. Aubrey Smith Professor of Accounting
John Robinson - Austin, TX
Work:
Restoration of Residential Properties
TDIndustries - Austin, TX
HVAC Maintenance Technician Hotsy Carlson Equipment - Austin, TX
Service Manager A & G Plumbing
Foreman
HVAC Maintenance Technician Hotsy Carlson Equipment - Austin, TX
Service Manager A & G Plumbing
Foreman
Education:
Texas State University - San Marcos, TX
Bachelor of Science in Technology Science Amarillo College - Amarillo, TX
Bachelor of Science in Technology Science Amarillo College - Amarillo, TX
Owner, Robinson Architects
Position:
Owner at Robinson Architects
Location:
Austin, Texas Area
Industry:
Architecture & Planning
Work:
Robinson Architects
-
Owner
Method And System For Optimizing Alignment Performance In A Fleet Of Exposure Tools
US Patent:
7679069, Mar 16, 2010
Filed:
Mar 15, 2007
Appl. No.:
11/686871
Inventors:
Michael E. Adel - Zichron Ya'akov, IL
John Robinson - Austin TX, US
Pavel Izikson - Haifa, IL
Brad Eichelberger - Dillsburg PA, US
Amir Widmann - Sunnyvale CA, US
Atsuhiko Kato - Tokyo, JP
John Robinson - Austin TX, US
Pavel Izikson - Haifa, IL
Brad Eichelberger - Dillsburg PA, US
Amir Widmann - Sunnyvale CA, US
Atsuhiko Kato - Tokyo, JP
Assignee:
KLA-Tencor Technologies Corporation - Milpitas CA
International Classification:
G21K 1/00
US Classification:
2504911, 2504921, 2504922, 2504923
Abstract:
A method for optimizing alignment performance in a fleet of exposure systems involves characterizing each exposure system in a fleet of exposure systems to generate a set of distinctive distortion profiles associated with each exposure system. The set of distinctive distortion profiles are stored in a database. A wafer having reference pattern formed thereon is provided for further pattern fabrication and an exposure system is selected from the fleet to fabricate a next layer on the wafer. Linear and higher order parameters of the selected exposure system are adjusted using the distinctive distortion profiles to model the distortion of the reference pattern. Once the exposure system is adjusted, it is used to form a lithographic pattern on the wafer.
Methods And Systems For Creating Or Performing A Dynamic Sampling Scheme For A Process During Which Measurements Are Performed On Wafers
US Patent:
2012020, Aug 16, 2012
Filed:
Apr 26, 2012
Appl. No.:
13/457383
Inventors:
Pavel Izikson - Haifa, IL
John Robinson - Austin TX, US
Mike Adel - Zichron Ya'akov, IL
Amir Widmann - Sunnyvale CA, US
Dongsub Choi - Bundang-ku Sungnam City, KR
Anat Marchelli - Migdal Haemek, IL
John Robinson - Austin TX, US
Mike Adel - Zichron Ya'akov, IL
Amir Widmann - Sunnyvale CA, US
Dongsub Choi - Bundang-ku Sungnam City, KR
Anat Marchelli - Migdal Haemek, IL
Assignee:
KLA-TENCOR CORPORATION - San Jose CA
International Classification:
H01L 21/66, G06F 19/00
US Classification:
438 5, 702 83, 700 97, 257E21525
Abstract:
Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one tot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.
Inspecting A Wafer And/Or Predicting One Or More Characteristics Of A Device Being Formed On A Wafer
US Patent:
2014003, Feb 6, 2014
Filed:
Mar 2, 2013
Appl. No.:
13/783291
Inventors:
Amir Widmann - Sunnyvale CA, US
Ellis Chang - Saratoga CA, US
John Robinson - Austin TX, US
Allen Park - San Jose CA, US
Ellis Chang - Saratoga CA, US
John Robinson - Austin TX, US
Allen Park - San Jose CA, US
International Classification:
G06T 7/00
US Classification:
382149
Abstract:
Methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer are provided. One method includes acquiring images for multiple die printed on a wafer, each of which is printed by performing a double patterning lithography process on the wafer and which include two or more die printed at nominal values of overlay for the double patterning lithography process and one or more die printed at modulated values of the overlay; comparing the images acquired for the multiple die printed at the nominal values to the images acquired for the multiple die printed at the modulated values; and detecting defects in the multiple die printed at the modulated values based on results of the comparing step.
Overlay Metrology And Control Method
US Patent:
7804994, Sep 28, 2010
Filed:
Feb 13, 2003
Appl. No.:
10/367124
Inventors:
Michael Adel - Zichron Ya'akov, IL
Mark Ghinovker - Migdal Haemek, IL
Elyakim Kassel - D.N. Misgav, IL
Boris Golovanevsky - Haifa, IL
John C. Robinson - Austin TX, US
Chris A. Mack - Austin TX, US
Jorge Poplawski - Haifa, IL
Pavel Izikson - Haifa, IL
Moshe Preil - Sunnyvale CA, US
Mark Ghinovker - Migdal Haemek, IL
Elyakim Kassel - D.N. Misgav, IL
Boris Golovanevsky - Haifa, IL
John C. Robinson - Austin TX, US
Chris A. Mack - Austin TX, US
Jorge Poplawski - Haifa, IL
Pavel Izikson - Haifa, IL
Moshe Preil - Sunnyvale CA, US
Assignee:
KLA-Tencor Technologies Corporation - Milpitas CA
International Classification:
G06K 9/00
US Classification:
382151, 382145, 430 22, 430 30, 356399, 356401
Abstract:
An overlay method for determining the overlay error of a device structure formed during semiconductor processing is disclosed. The overlay method includes producing calibration data that contains overlay information relating the overlay error of a first target at a first location to the overlay error of a second target at a second location for a given set of process conditions. The overlay method also includes producing production data that contains overlay information associated with a production target formed with the device structure. The overlay method further includes correcting the overlay error of the production target based on the calibration data.
Unique Mark And Method To Determine Critical Dimension Uniformity And Registration Of Reticles Combined With Wafer Overlay Capability
US Patent:
2011005, Mar 3, 2011
Filed:
Jun 21, 2010
Appl. No.:
12/819281
Inventors:
DongSub Choi - Sungnam City, KR
Amir Widmann - Sunnyvale CA, US
Zain Saidin - San Mateo CA, US
Frank Laske - Weilburg, DE
John Robinson - Austin TX, US
Amir Widmann - Sunnyvale CA, US
Zain Saidin - San Mateo CA, US
Frank Laske - Weilburg, DE
John Robinson - Austin TX, US
Assignee:
KLA-TENCOR CORPORATION - Milpitas CA
International Classification:
G01B 11/14
US Classification:
356620
Abstract:
A combined metrology mark, a system, and a method for calculating alignment on a semiconductor circuit are disclosed. The combined metrology mark may include a mask misregistration structure and a wafer overlay mark structure.
John Robinson
Location:
Austin, Texas Area
Industry:
Semiconductors