JOHN EUGENE AMATO
Pilots at Redbridge Rd, Tracy, CA

6645815, Nov 11, 2003

Nov 20, 2001

10/010483

Fwu-Iuan Hshieh - Saratoga CA
Koon Chong So - Fremont CA
John E. Amato - Tracy CA
Brian D. Pratt - Tracy CA

General Semiconductor, Inc. - Melville NY

H01L 21336

438270, 148DIG 126

A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask over the epitaxial layer, wherein the patterned implantation mask comprises a patterned insulating region and covers at least a portion of the source regions, and wherein the patterned implantation mask has apertures over at least portions of the epitaxial layer adjacent the source regions; (b) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of a second conductivity type at a first energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from an upper surface of the epitaxial layer; (c) forming deep dopant regions by a process comprising: (1) implanting a second dopant of the second conductivity type at a second energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the second dopant at elevated temperatures to a second depth from the upper surface of the epitaxial layer; and (d) enlarging apertures in the patterned insulating region. In this method, the second energy level is greater than the first energy level, the second depth is greater than the first depth, and the first and second dopants can be the same or different. The method of the present invention can be used, for example, to form a device that comprises a plurality of trench MOSFET cells.

6657254, Dec 2, 2003

Nov 21, 2001

09/999116

Fwu-Iuan Hshieh - Saratoga CA
Koon Chong So - Fremont CA
John E. Amato - Tracy CA
Yan Man Tsui - Union City CA

General Semiconductor, Inc. - Melville NY

H01L 2976

257330, 257329, 257341, 257342

A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench. The presence of the doped region lying between the bottom portion of the trench and the substrate (also referred to herein as a “trench bottom implant”) serves to reduce the on-resistance of the device.

6657255, Dec 2, 2003

Oct 30, 2001

10/021419

Fwu-Iuan Hshieh - Saratoga CA
Koon Chong So - Fremont CA
William John Nelson - Danville CA
John E. Amato - Tracy CA

General Semiconductor, Inc. - Melville NY

H01L 2976

257330, 257332, 257331, 257329

A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

6630402, Oct 7, 2003

Nov 21, 2001

09/990460

Fwu-Iuan Hshieh - Saratoga CA
Koon Chong So - Fremont CA
John E. Amato - Tracy CA

General Semiconductor, Inc. - Melville NY

H01L 2100

438692, 216 38, 216 75, 216 78, 216 88, 438720, 438745, 438754

In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.

7015125, Mar 21, 2006

Nov 8, 2004

10/983490

Fwu-Iuan Hshieh - Saratoga CA, US
Koon Chong So - Fremont CA, US
John E. Amato - Tracy CA, US
Yan Man Tsui - Union City CA, US

General Semiconductor, Inc. - Melville NY

H01L 21/4763, H01L 21/336, H01L 21/8242

438589, 438268, 438269, 438637, 438255

A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

7049194, May 23, 2006

Dec 1, 2003

10/725326

Fwu-Iuan Hshieh - Saratoga CA, US
Koon Chong So - Fremont CA, US
William John Nelson - Danville CA, US
John E. Amato - Tracy CA, US

General Semiconductor, Inc. - Melville NY

H01L 21/336

438259, 438270, 438271

A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

7094640, Aug 22, 2006

Dec 1, 2003

10/725325

Fwu-Iuan Hshieh - Saratoga CA, US
Koon Chong So - Fremont CA, US
John E. Amato - Tracy CA, US
Yan Man Tsui - Union City CA, US

General Semiconductor, Inc. - Melville NY

H01L 21/8238, H01L 21/336

438212, 438259, 438270, 438271

A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent the insulating layer and forming a source region of said first conductivity type within an upper portion of the body region and adjacent the trench.

2005004, Feb 24, 2005

Aug 22, 2003

10/647029

John Amato - Tracy CA, US
Badredin Fatemizadeh - San Jose CA, US
Ali Salih - Mesa AZ, US
Shamsul Khan - Santa Clara CA, US

H01L029/76

257330000

A closed cell trench power MOSFET has a trench () running in first and second perpendicular directions through a body region () and extending into an epitaxial region (). The trenches meet to form intersections (). A polysilicon layer () is deposited in the trench. A photoresist pattern () is formed over the intersections to inhibit removal of the conductive material from the trench in and around the intersection areas. The process of inhibiting removal of the conductive material over the intersection areas of the trench prevents formation of a depression in the polysilicon in and around the intersection which would increase resistivity in the gate region. The goal of preventing formation of depressions in the polysilicon can also be achieved by making the polysilicon thicker on the intersections prior to the etching process and by making the trenches narrower in and around the intersections.

8581376, Nov 12, 2013

Jun 18, 2010

12/819111

Hamza Yilmaz - Saratoga CA, US
Xiaotian Zhang - San Jose CA, US
Yan Xun Xue - Los Gatos CA, US
Anup Bhalla - Santa Clara CA, US
Jun Lu - San Jose CA, US
Kai Liu - Mountain View CA, US
Yueh-Se Ho - Sunnyvale CA, US
John Amato - Tracy CA, US

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/44, H01L 21/31

257676, 257686, 257777

The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

2014005, Feb 27, 2014

Nov 4, 2013

14/071626

Xiaotian Zhang - San Jose CA, US
Yan Xun Xue - Los Gatos CA, US
Anup Bhalla - Santa Clara CA, US
Jun Lu - San Jose CA, US
Kai Liu - Mountain View CA, US
Yueh-Se So - Sunnyvale CA, US
John Amato - Tracy CA, US

ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED - Sunnyvale CA

H01L 23/495

257669

The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.