MR. JOHN E BAUER, M.D.
Osteopathic Medicine at Broadway St, Portland, OR

6789037, Sep 7, 2004

Feb 14, 2001

09/784255

Stephen H. Gunther - Beaverton OR
Frank Binns - Hillsboro OR
Jack D. Pippin - Portland OR
Linda J. Rankin - Portland OR
Edward A. Burton - Hillsboro OR
Douglas M. Carmean - Beaverton OR
John M. Bauer - Portland OR

Intel Corporation - Santa Clara CA

G01K 710

702132

An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

5715428, Feb 3, 1998

Apr 29, 1996

8/639719

Wen-Hann Wang - Portland OR
Konrad K. Lai - Aloha OR
Gurbir Singh - Portland OR
Michael W. Rhodehamel - Beaverton OR
Nitin V. Sarangdhar - Beaverton OR
John M. Bauer - Portland OR
Mandar S. Joshi - Beaverton OR
Ashwani K. Gupta - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 1300

395468

A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache. A read or a write to a line in I state results in a cache miss. The present invention associates states with lines and defines rules governing state transitions.

5701503, Dec 23, 1997

Dec 21, 1994

8/360331

Gurbir Singh - Portland OR
Wen-Hann Wang - Portland OR
Michael W. Rhodehamel - Beaverton OR
John M. Bauer - Portland OR
Nitin V. Sarangdhar - Portland OR

Intel Corporation - Santa Clara CA

G06F 1200

395800

A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer. When the processor has transferred the entire cache line to the L2 cache memory, the processor signals the L2 cache memory to transfer the contents of the chunk write buffer into the data array of the cache memory.

5604753, Feb 18, 1997

Jan 4, 1994

8/177861

John M. Bauer - Portland OR
Glenn J. Hinton - Portland OR
Gregory P. Meece - Beaverton OR
David B. Papworth - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 1110

371 401

A method and apparatus for performing error correction on data from an external memory is described. The present invention includes a method and apparatus for receiving data from an external memory source and determining if the data has an error. The data is forwarded to the requesting unit while the error correction is performed on the data, such that the two operations are performed in parallel. The present invention also includes a method and apparatus for subsequently correcting data if a single bit error exists. The corrected data is then forwarded to the requesting unit during the next cycle. Also if an error is detected, the present invention produces an indication to the device. The device is flushed in response to the indication.

6980918, Dec 27, 2005

Apr 9, 2004

10/821292

Stephen H. Gunther - Beaverton OR, US
Frank Binns - Hillsboro OR, US
Jack D. Pippin - Portland OR, US
Linda J. Rankin - Portland OR, US
Edward A. Burton - Hillsboro OR, US
Douglas M. Carmean - Beaverton OR, US
John M. Bauer - Portland OR, US

Intel Corporation - Santa Clara CA

G06F015/00

702132

An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.

5809524, Sep 15, 1998

Mar 24, 1997

8/822044

Gurbir Singh - Portland OR
Wen-Hann Wang - Portland OR
Michael W. Rhodehamel - Beaverton OR
John M. Bauer - Portland OR
Nitin V. Sarangdhar - Portland OR

Intel Corporation - Santa Clara CA

G06F 1212

711118

A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.