JOHN DOUGLAS HUDSON, M.D.
Psychiatric at Parkcrest Dr, Austin, TX

License number

Texas D0915

Professional information

Principal Design Engineer At Arm

Position:

Principal Design Engineer at ARM

Location:

Austin, Texas Area

Industry:

Semiconductors

Work:

ARM - Austin, Texas Area since Jun 2004 - Principal Design Engineer Obsidian Software - Austin, Texas Area Jan 2003 - Oct 2003 - Validation Engineer ARM - Austin, Texas Area Jun 1998 - Jan 2003 - Senior Design Engineer Motorola INC - Austin,Tx Aug 1991 - Jun 1998 - Design Engineer

Education:

University of Illinois at Urbana-Champaign 1987 - 1990
Bachelor of Science (B.S.), Electrical and Electronics Engineering

John Douglas Hudson, Austin TX

Specialties:

Neurologist

Address:

5508 Parkcrest Dr, Austin, TX 78731

Education:

University of Texas Medical Branch, School of Medicine - Doctor of Medicine

Board certifications:

American Board of Psychiatry and Neurology Certification in Neurology (Psychiatry and Neurology)

System And Method For Recovering A Microprocessor From A Locked Bus State

US Patent:

5961622, Oct 5, 1999

Filed:

Oct 23, 1997

Appl. No.:

8/956966

Inventors:

John Michael Hudson - Austin TX
Donald L. Tietjen - Austin TX
Terry L. Biggs - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1336, G06F 946

US Classification:

710107

Abstract:

A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists. In response to the signal (30) and the bit (270), the locked bus (one or more of busses 22, 24, and/or 26) will attempt to recover from the locked bus state.

Method For Testing A Test Architecture Within A Circuit

US Patent:

5517637, May 14, 1996

Filed:

Dec 9, 1994

Appl. No.:

8/352934

Inventors:

William C. Bruce - Austin TX
Joseph E. Drufke - Austin TX
Chema O. Eluwa - Kyle TX
John M. Hudson - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G01R 3128

US Classification:

395500

Abstract:

A method for testing a test architecture in a circuit is accomplished by receiving or generating, based on the topology information for the circuit, a Boundary Scan Description Language (BSDL) description of the test architecture which is then verified for correct syntax, consistency, and standard compliance. Next, one or more tests are selected from a predetermined set of test methodologies, based on the type of testing to be performed. Self-checking test parameters are generated based on the BSDL description and the selected tests. Using these test parameters, a logic simulation algorithm tests the test architecture of the circuit and generates a report detailing any errors that are discovered.