John David Giles
Architects in Bountiful, UT

5542056, Jul 30, 1996

Oct 17, 1995

8/544364

Brent E. Jaffa - Sandy UT
Wayne D. Bell - Bountiful UT
John P. Giles - Bountiful UT

Unisys Corporation - Blue Bell PA

G06F 1340

395306

A bridge circuit includes a microprocessor having a first I/O port which couples to a SCSI bus and a second I/O port which is coupled through transceivers to an EISA bus. Also, the bridge circuit includes an EISA interface controller, having control lines coupled to the EISA bus and the transceivers, which enable the microprocessor to request and use the EISA bus in time-shared fashion. In order to achieve a high speed of operation, the bridge circuit further includes a memory module, coupled via a private bus to the second I/O port of the microprocessor, which sends instructions on the private bus directly to the microprocessor, without generating any signals on the EISA bus. In addition, in order to prevent deadlocks on the private bus, the bridge circuit includes a deadlock prevention circuit which is coupled to the microprocessor and the private bus and the EISA interface controller. This deadlock prevention circuit detects the occurrence of a predetermined event during a series of data transmissions between the microprocessor and the EISA bus. When such detection occurs, the deadlock prevention circuit directs the microprocessor to stop the series data transmissions over the EISA bus and private bus before the end of the series; and it directs the microprocessor to not restart the series on the private bus until after the EISA bus is required.