JOHN CHARLES BUSH
Pilots at Ctr St, Leander, TX

6380554, Apr 30, 2002

Jun 8, 1998

09/093358

John J. Bush - Leander TX
Mark I. Gardner - Cedar Creek TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2358

257 48, 257758

The present invention advantageously provides a test structure and method for using electrical measurements to determine the overlay between successive layers of conductors lithographically patterned upon a semiconductor topography. According to an embodiment, a test structure is provided which includes first, second, and third conductive structures having first, second, and third corner regions, respectively. Alternatively, the conductive structures may include only a single conductive structure having three corner regions. Each corner region is bounded by a pair of outer lateral edges configured substantially perpendicular to one another. First, second, and third conductors are operably coupled to the first, second, and third corner regions, respectively, such that overlapping areas of the conductors arranged directly above the corner regions are substantially rectangular in shape. The layout design for the test structure specifies the targeted dimensions, x and y, of each overlapping area. Fabrication of the test structure may result in the overlapping areas being shifted from their targeted positions such that their dimensions are larger or smaller than their targeted values.

6469316, Oct 22, 2002

Jan 8, 2001

09/756523

John J. Bush - Leander TX
Mark I. Gardner - Cedar Creek TX
David E. Brown - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2358

257 48, 257401

Various embodiments of a test circuit and methods of fabricating and using the same are provided. In one aspect, a test circuit includes a semiconductor substrate and a mask thereon that has an opening to enable impurity doping of selected portions of the test circuit. A plurality of circuit devices are provided on the substrate that have respective active regions positioned at staggered known distances from the mask opening. Each of the plurality of circuit devices has a gate electrode that extends to the opening and has a first impurity region of a first conductivity type and a second impurity region of a second and opposite conductivity type. Where the predicted on-state output current of a given circuit device exceeds an actual output current of the given circuit device, there is indication of an overlap between the first and second impurity regions of the gate electrode of the given device.

6359461, Mar 19, 2002

Feb 10, 1998

09/021094

John J. Bush - Leander TX
Jon D. Cheek - Round Rock TX
H. Jim Fulford - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 3126

324769, 324768

The present invention advantageously provides a test structure and method for determining the distinct characteristics of each transistor arranged in a densely packed configuration with other transistors. Formation of the test structure first involves forming gate conductors according to the configuration of the semiconductor topography whose device properties are being determined. That is, closely spaced gate conductors having relatively small lateral widths, i. e. , physical gate lengths, are formed above a semiconductor substrate. All of the gate conductors except the one being tested are then etched from above the substrate. Source/drain implants which are self-aligned to the opposed sidewall surfaces of the gate conductor retained above the substrate are forwarded into the substrate. Absent the other gate conductors, the resulting source/drain regions may each have a larger lateral width greater than the distance between the pre-existing gate conductors. As such, the lateral width of contacts formed through an interlevel dielectric to the source/drain regions may be made significantly less than the lateral width of each source/drain region.

6429052, Aug 6, 2002

Nov 13, 2000

09/711401

Mark I. Gardner - Cedar Creek TX
John J. Bush - Leander TX
Frederick N. Hause - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 218232

438142

The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or “t-shaped” gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, forming a layer of polysilicon above the gate insulation layer, forming a layer of amorphous silicon above the layer of polysilicon, and patterning the layer of polysilicon and the layer of amorphous silicon to define a gate structure. The method further comprises reducing the width of the layer of polysilicon and the layer of amorphous silicon by performing an oxidation process, whereby the layer of polysilicon has a post-oxidation width that is less than the post-oxidation width of the layer of amorphous silicon, and forming a plurality of source/drain regions in the substrate adjacent the gate electrode of the device.

6110786, Aug 29, 2000

Apr 16, 1998

9/061409

Mark I. Gardner - Cedar Creek TX
Jon Cheek - Round Rock TX
John Bush - Leander TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438300

A semiconductor device having an elevated gate electrode and elevated active regions and a process for manufacturing such a device is disclosed. In accordance with one embodiment a semiconductor device is formed by forming a gate insulating layer over a substrate and forming a photoresist block over the gate insulating layer. First portions of the gate insulating layer and first portions of the substrate adjacent the photoresist block are then removed to form a first elevated substrate region under the gate insulating layer and photoresist block. Edge portions of the photoresist block are then removed. Second portions of the gate insulating layer and portions of the first elevated substrate region adjacent the photoresist block are then removed to form second elevated substrate regions adjacent the photoresist block, and a dopant is implanted into the second elevated substrate regions to form source/drain regions, and the photoresist block is used to form a gate electrode. In accordance with another embodiment a semiconductor device is formed substantially as above, but the dopant is implanted at an angle relative to the substrate surface.

5986283, Nov 16, 1999

Feb 25, 1998

9/030751

John J. Bush - Leander TX
Jon D. Cheek - Round Rock TX
Mark I. Gardner - Cedar Creek TX

Advanced Micro Devices - Sunnyvale CA

H01L 2358, G01R 3126

257 48

The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners. Further, lithographic patterning may lead to a reduction in the lengths of the gate conductors and the conductors.

6130454, Oct 10, 2000

Jul 7, 1998

9/111053

Mark I. Gardner - Cedar Creek TX
John J. Bush - Leander TX
Jon D. Cheek - Round Rock TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2978

257330

A process is provided for forming a gate conductor within a trench having opposed sidewalls which approach each other as they pass from the upper surface of a semiconductor substrate to the floor of the trench. According to an embodiment, an opening is formed through a masking layer residing upon the substrate to expose the portion of the substrate to be etched during trench formation. The opening is created using optical lithography and an etch technique. As such, the minimum width of the opening is limited in size. Once the trench has been etched in the substrate, dielectric sidewall spacers may be formed upon the sidewalls of the trench and the lateral boundaries of the masking layer. A gate conductor is subsequently formed between the sidewall spacers. The lateral width of the resulting gate conductor is thus dictated by the distance between the sidewall spacers, and hence by the thickness of the spacer material deposited upon the sidewalls of the trench.

6191446, Feb 20, 2001

Mar 4, 1998

9/035780

Mark I. Gardner - Cedar Creek TX
John J. Bush - Leander TX
Jon D. Cheek - Round Rock TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2976, H01L 31062

257330

A process is provided for forming a transistor in which the channel length is controlled by the depth of a trench etched into a semiconductor substrate. A masking layer extending across the substrate and a portion of the substrate are etched simultaneously to form the trench. A gate dielectric is formed upon the opposed sidewall surfaces of the trench. A pair of gate conductors are then formed upon the exposed lateral surfaces of the gate dielectric and the masking layer. Subsequently, an unmasked region of the substrate underneath the trench is implanted with dopant species and then annealed to form a source junction. The anneal temperature is preferably sufficient to cause the dopant species in the source junction to migrate laterally past the opposed sidewall surfaces of the trench. Drain junctions may subsequently be formed within the substrate a spaced distance above the source region on opposite sides of the trench. The physical channel length of the resulting transistors is thus defined as the distance between a source region and an overlying drain region.

6075417, Jun 13, 2000

Jan 5, 1998

9/002655

Jon Cheek - Round Rock TX
Antonio Garcia - Austin TX
John Bush - Leander TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H03B 524, G01R 3100

331 44

An improved oscillator test structure is disclosed. A structure according to one embodiment includes an odd plurality of first transistor pairs formed on a predetermined area of a semiconductor substrate. The transistor pairs are electrically connected in a serial ring. The structure also includes at least one second transistor pair, also formed within the predetermined area on the substrate, but electrically isolated from the odd plurality of first transistor pairs.

6977195, Dec 20, 2005

Aug 16, 2004

10/919119

John J. Bush - Leander TX, US
Wen-Jie Qi - Austin TX, US
Robert Dawson - Austin TX, US

FASL, LLC - Sunnyvale CA

H01L021/336, H01L021/8234

438197, 438224, 438227

For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the center junction adjacent the isolation structure. A junction silicide is formed with the center and periphery junctions. The magnitude of a reverse-bias voltage across the junction silicide and the P-well is incremented for determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.