Position:
Device Modeling and Characterization Engineer at Freescale Semiconductor
Work:
Freescale Semiconductor
since Jul 2006
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Device Modeling and Characterization Engineer
Motorola
Oct 2000 - Oct 2005
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Device Modeling Engineer
Motorola
Feb 1998 - Oct 2000
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Device Engineer
Cypress Semiconductor
Jun 1994 - Jul 1996
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Process Engineer
Education:
Purdue University 1996 - 1998
MS, Engineering (EE)
Purdue University 1990 - 1994
BS, Chemical Engineering
Interests:
Photography, Bird Watching, Billiards, Golf, Basketball, Astronomy
Honor & Awards:
Publications:
John Hughes, Gerold Neudeck, Reha Uzsoy, “Effects of Epitaxial Silicon on the Manufacturing Performance of Wafer Fabrication Lines,” IEEE International Electronics Manufacturing Technology Symposium, 1998
John Hughes, et al., "Dry Etch Sequencing Induced Gate Oxide Degradation Due to Metallic Contamination In 0.25 um CMOS Manufacturing," IEDM, 1998
Mathew, et al., “Multi Gated Device architectures advances, advantages, and challenges,” IEEE International Conference on Integrated Circuit Design and Technology, 2004
Mathew, et al., “CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET),” IEEE International SOI Conference, 2004
Thean, et al., “Performance and Reliability of Sub-100nm TaSiN Metal Gate Fully-Depleted SOI Devices with High-K (HfO2) Gate Dielectric,” Symposium on VLSI Technology Digest of Technical Papers,” 2004